SPRADO2A November 2024 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1
MCU_PORz is the external MCU and Main Domain cold reset input to the processor. The recommendation is to hold the MCU_PORz pulled low during the supply ramp and oscillator start-up. Follow the recommended MCU_PORz timing in the Power-Up Sequencing diagram of the processor-specific data sheet.
For the MCU_PORz (3.3V tolerant, fail-safe input), apply a 3.3V input. The input thresholds are a function of the 1.8V IO supply voltage (VDDS_OSC0).
Not connecting a valid MCU_PORz can cause unpredictable and random behavior. Because the device is not going through a valid reset, internal circuits are in random states. Slow rising reset signal causes glitches internal to the processor reset circuit. Use a fast rise time discrete push-pull output as MCU_PORz input and add a low capacitance value (22pF) filter provision.
When PMIC is used, connect the output from push-pull output type logic gate or discrete buffer (with fast rise time) as an MCU_PORz input, rather than a slow rising open-drain output (can glitch internally).
Provision to connect a filter capacitor at the MCU_PORz input is recommended. The capacitor value and mounting is use-case dependent. Verify the capacitor value does not cause the LVCMOS input to violate the slew rate requirements or glitch internally due to slow ramp.
Refer to the silicon errata advisory i2407- RESET. MCU_RESETSTATz is unreliable when MCU_RESETz is asserted low.
Connect external warm reset inputs MCU_RESETz and RESET_REQz as per the Pin Connectivity Requirements section of the processor-specific data sheet. Warm reset inputs (LVCMOS inputs) have input slew rate requirements. Connecting a capacitor directly at the input is not recommended due to the slow input ramp. A schmitt trigger-based debouncing circuit is recommended. For implementing the debouncing logic, see the processor-specific SK schematic.