SPRADO2A November 2024 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1
Many of the TI EPHYs configure the outputs as inputs during reset and captures the configuration (Pin strapping is done through resistors) information on strap inputs when the processor is released from reset. Appropriate pullup or pulldown may need to be applied to strap inputs (IOs) that also connect to processor IOs. TI EPHYs used on the device-specific SK use a combination of pullup and pulldown allowing multiple configuration modes to be configured using each pin. During processor reset, the IO buffers and internal pullup or pulldown are disabled, which minimizes any concern of a mid-supply potential being applied to the processor input buffer by the EPHY. The EPHYs are required to be configured to normal state from reset state to take care the EPHY is driving a valid logic state before enabling any of the associated processor input buffers.