General
Review and verify the following for
the custom schematic design:
- Above sections, including
relevant application notes and FAQ links
- Pin attributes, signal
description, and electrical specifications
- Electrical characteristics
and additional available information
- A valid fixed supply source is connected to
(VDDSHV_CANUART, VDDSHV_MCU, VDDSHV0, VDDSHV1,
VDDSHV2, VDDSHV3) all the IO supply groups as per
the ROC
- A valid supply (that can be dynamically changed)
source is connected to VDDSHV4, VDDSHV5, VDDSHV6 IO
supply group as per the ROC
- Slew rate requirements for IO
supply rails are followed
- Internal LDO output pins have
the recommended capacitors connected (across CAP_VDDSn pin and VSS)
- Power sequence
recommendations as per the processor data sheet are followed
Schematics Review
Follow the below list for the custom
schematic design:
- Connection of the recommended
capacitor to CAP_VDDSn pins and VSS
- CAP_VDDSn capacitor package
(use the smallest possible (0201 or greater package possible which is
closest to 0201) package to minimize loop inductance)
- Voltage rating of the
capacitor selected for the capacitance value to be in the range 0.8 to 1.5μF
including aging, temperature and DC bias effect
- All IO supply rails have a
valid supply irrespective of the use of the IOs referenced to the IO supply
group
- Supply rails connected follow
the ROC
- Each CAP_VDDSn pin requires a
separate 1μF capacitor connected with respect to VSS (ground)
- Select CAP_VDDSn capacitor
with less the 1Ω ESR, keep the trace loop inductance to < 2.5nH
Additional
- For all supply rails, use a 0Ω
resistor or jumper for isolation or current measurement at the output of the
supply rails.
- When any of the VDDSHVx power
rails are sourced from the 3.3V supply, all IOs referenced to the IO supply
group VDDSHVx must operate at 3.3V levels. If a VDDSHVx power rail is sourced
from a 1.8V supply, all IOs referenced to the IO supply group VDDSHVx must
operate at 1.8V levels.
- Some interfaces span multiple
VDDSHVx IO supply groups, for example MMC2 and GPMC. When using one of the
interfaces, all VDDSHVx domains supporting a specific interface need to share
the same voltage source.
- Most processor IOs are not
fail-safe. Applying input voltage to the IOs while the corresponding IO power
domain (VDDSHVx) is off is not allowed or recommended.
- Verify all IO pins on each VDDSHVx (or
VDDSHV_MCU) supply only support one voltage level.
- Follow the processor-specific SK
for implementation of ferrites and capacitors.
- Leaving VDDSHV5
power supply rail unconnected is not recommended. Connect
the power pins to either 1.8V or 3.3V, depending on your
preference for the voltage level of the VDDSHV5 IO bank
signals.