General
Review and verify the following for
the custom schematic design:
- Above sections, including
relevant application notes and FAQ links.
- Pin attributes, signal
description, and electrical specifications.
- Electrical characteristics,
timing parameters, and any additional available information.
- MMC0 interface is compliant with
the JEDEC eMMC electrical standard v5.1 (JESD84-B51)
- AM62Ax and AM62Dx processor families implements a
soft PHY. The pulls required for DAT0, clock, and control signals are
recommended to be implemented externally.
- Include a series resistor (0Ω) on
MMC0_CLK placed as close to processor clock output pin as possible to dampen
reflections. MMC0_CLK is looped back internally on read transactions, and the
resistor eliminates possible signal reflections, which cause false clock
transitions. Use 0Ω initially and adjust as required to match the PCB trace
impedance.
- Add pullups (10kΩ or 47kΩ) for
DAT0 and CMD signals. Connect the pullup to the IO supply group VDDSHV4 (MMC IO
rail). For DAT1-7 eMMC device is expected to have the pullups enabled during
reset. The eMMC host/PHY disables the eMMC device pullups and enables processor
internal pullups. Provision for external pullups is optional, or delete the
pullups.
- VDDSHV4 (1.8V or 3.3V) and the
attached eMMC device IO supply is required to be powered from the same power
source.
- Add a pulldown (10kΩ) to the eMMC
attached device clock input near to the attached device.
- For implementing eMMC device reset, use a 2-input
ANDing logic when the memory is used for boot. Connect RESETSTATz as one of the
inputs and processor IO as another input. Add a pullup for the processor IO
input near the AND gate input pin and an isolation resistor near to the
processor IO output. Alternatively, RESETSTATz is used as the reset source. When
RESETSTATz is used as the reset source, verify the voltage level compatibility
with the eMMC IO supply. Use a level shifter as required.
- When eMMC boot is not required,
the eMMC attached device reset can be controlled by the processor IO. The
recommendation is to pulldown the reset of the eMMC memory device during board
power reset.
- Add additional decoupling
capacitors for attached memory device as required. Refer SK-AM62P-LP
schematics.
Schematic Review
Follow the below list for the custom
schematic design:
- Required bulk and decoupling
capacitors are provided for processor and attached device rails. Compare with
the SK schematics
- Pull values for the data,
command, and clock signals. Compare with the relevant SK
- Series resistor value and
placement on the clock output signal near to the processor clock output
- Implementation of reset logic
including the IO level compatibility. Adding a capacitor at the reset input of
eMMC attached device is not recommended when RESETSTATz or processor IO is
connected directly to control the reset. A stand-alone reset connection to reset
the eMMC memory device is not recommended
- Supply rails connected follow the
ROC
Additional
- Connect an external pulldown on CLK, and external
pullups on CMD and DAT0 to prevent the eMMC device inputs from floating until
software initializes the host controller and processor IOs associated with MMC0.
The eMMC standard mandates that eMMC devices have internal pullups enabled
during reset on DAT1-7, external pullups are not required for DAT1-7 signals.
Software turns on the respective internal DAT pullups when the bus width is
increased from 1-bit mode to 4-bit or 8-bit mode. External pulls are required
because the IOs associated with MMC0 are implemented with standard dual-voltage
LVCMOS IO cells with the capability of multiplexing additional signal functions
to the respective device pins. MMC0 IOs buffers are off during reset as what
interface is connected to MMC0 pins is unknown.
- Verify eMMC_RSTn reset input is enabled in the
eMMC device (eMMC non-volatile configuration space) for the reset logic to be
functional. Software can reset the attached device (eMMC, OSPI, SD card or EPHY)
without resetting the entire processor using the GPIO reset option, allowing for
a peripheral-specific reset in cases where the peripheral becomes unresponsive.
Eliminate the GPIO option and use the reset output, either warm or cold.
Software forces a warm reset if the peripheral becomes unresponsive. However,
using warm reset resets the entire device, rather than trying to recover the
specific peripheral without resetting the entire device. When RESETSTATz is used
to reset the attached device, verify the IO voltage level of the attached device
matches the RESETSTATz IO voltage level. A level translator is recommended to
match the IO voltage level. Alternatively, use a resistor divider and select an
optimum impedance value. A slow rise or fall time of the eMMC reset input causes
too much delay. Low reset input causes the processor to source too much
steady-state current during normal operation.
- ANDing logic additionally
performs level translation. Verify the reset IO level compatibility before
optimizing the reset ANDing logic. IO level mismatch can cause supply leakage
and affect processor operation
- Pulldown is selected for eMMC, SD card, or other
peripherals as there are cases where the clock is stopped or paused in a low
logic state and the pulldown option is consistent with the logic state.