As Figure 1-2 shows, the boot flow process is a sequence adopted by AM263P that starts upon
power-on. ROM code on the R5F is set to work in a certain way which is described in
the Initialization chapter of the device-specific Technical Reference Manual. The
ROM code expects specific instructions from the flash and expects specific timing
and framing configurations for establishing communication. Multiple boot modes are
supported in the AM263P device, and ROM code expects the following support:
- Flash device must operate in the
3.3V vicinity
- In OSPI boot mode, the flash must
support Octal Output Fast Read (opcode 0x8B) and the 1S-1S-8S transfer
protocol
- In QSPI boot mode, the flash must
support Quad Output Fast Read (opcode 0x6B) and the 1S-1S-4S transfer
protocol
- Flash device must allow 8
dummy clock cycles for setting up the initial address during the
previously-mentioned read operations
- Flash device must boot in 1S mode
by default
- Flash must support 3-byte
(24-bit) addressing mode by default
- Flash memory size 4MB is
recommended as a minimum
- Due to device errata item
i2426, the boot ROM does not support devices that use an extended
opcode. This issue only applies to flash memories that need extended opcode
support in 8D boot mode. 1S and 8S boot modes are not impacted by this
limitation. Support for this feature is planned for future device
revisions.
All of this information is available
in the data sheet of the flash device being evaluated. A flash device must support
all of the points mentioned above to meet AM263P compatibility requirements.