SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The Control Register allows setup and control of the PDSP as shown in Figure 4-36.
31 | 16 | 15 | 14 | 13 | 9 | 8 | 7 | 4 | 3 | 2 | 1 | 0 |
PC_RESET | STATE | BIG | Reserved | STEP | Reserved | C_EN | SLP | P_EN | S_RST |
R/W-0 | R-0 | R-0 | R-0 | R/W-0 | R--0 | R/W-0 | R/W-0 | R/W-0 | R-0 |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Bits | Field | Description |
---|---|---|
31-16 | PC_RESET | Program Counter Reset Value: This field controls the address where the PDSP will start executing code from after it is taken out of reset. |
15 | STATE | Run State: This bit indicates whether the PDSP is currently executing an instruction or is halted.
This bit is used by an external debug agent to know when the PDSP has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the P_EN has been cleared. |
14 | BIG | Big Endian state. Returns the mode that the PDSP is in.
|
13-9 | Reserved | Reads return 0 and writes have no effect |
8 | STEP | Single Step Enable - This bit controls whether or not the PDSP will execute only a single instruction when enabled.
Note that this bit does not actually enable the PDSP, it only sets the policy for how much code will be run after the PDSP is enabled. The P_EN bit must be explicitly asserted. It is expressly legal to initialize both the STEP and P_EN bits simultaneously. (Two independent writes are not required to cause the stated functionality.) |
7-4 | Reserved | Reads return 0 and writes have no effect |
3 | C_EN | Cycle counter enable - Enables PDSP cycle counters
|
2 | SLP | Processor sleep indicator - This bit indicates whether or not the PDSP is currently asleep.
If this bit is written to a 0, the PDSP will be forced to power up from sleep mode. |
1 | P_EN | Processor Enable - This bit controls whether or not the PDSP is allowed to fetch new instructions
If this bit is de-asserted while the PDSP is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PDSP pauses execution. Otherwise, the PDSP will halt immediately. Because of the unpredictability/timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PDSP is currently running. The STATE bit should be consulted for an absolute indication of the run state of the core. When the PDSP is halted, it's internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PDSP will resume processing exactly where it left off in the instruction stream. |
0 | S_RST | Soft reset — when this bit is cleared, the PDSP will be reset. This bit is set back to 1 on the next cycle after it has been cleared. |