4.4.1.2 End Of Interrupt (EOI) Register (0x00000010)
The EOI Register (Figure 4-41) allows software to clear specific interrupts within the INTD module. Unless interrupts have been cleared, they will not trigger again. Each interrupt within the QMSS is cleared by writing a specific 8-bit value to the register. Writing to this register does not clear corresponding bits in the Status Registers, nor does it clear interrupts within the CorePac’s interrupt controller. When the EOI is written, the interrupt will trigger again if the corresponding Int Count Register is not 0, (this should not happen with firmware generated interrupts).
Figure 4-41 EOI Register (0x00000010)
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Table 4-72 EOI Register Field Descriptions
Bit |
Field |
Description |
30-8 |
Reserved |
Reads return 0 and writes have no effect |
7-0 |
INT_VAL |
Valid values are: (other values are ignored)
- 0, 1 = PKTDMA RX starvation interrupts 0 and 1 (respectively)
- 2 - 33 = High-priority channel interrupts 0 through 31 (respectively)
- 34 - 49 = Low-priority channel interrupts 0 through 15 (respectively)
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