SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
Table 4-70 shows registers within the INTD config region.
Offset | Name | Description |
---|---|---|
0x00000000 | Revision Register | The Revision Register contains the major and minor revisions for the INTD module. |
0x00000010 | End of Interrupt Register | The EOI Register allows software to clear specific interrupts within the INTD module. Unless interrupts have been cleared, they will not trigger again. Each interrupt within QMSS is cleared by writing a specific 8-bit value to the register. Writing to this register does not clear corresponding bits in the Status Registers, nor does it clear interrupts within the CorePac’s interrupt controller. When the EOI is written, the interrupt will trigger again if the corresponding Int Count Register is not 0, (this should not happen with firmware generated interrupts). |
0x00000200, 204, 208, 20c, 210 | Status Registers 0, 1, 2, 3, 4 | An array of five registers that provide status on the interrupts managed by the INTD. Registers 2 and 3 are not used in the QMSS INTD. Registers 0, 1, and 4 expose one bit per QMSS interrupt (see each individual register layout). Reading the registers returns a 1 bit for each interrupt that has been triggered. Writing to the registers causes an interrupt to be triggered for each set (1) bit just as if the corresponding input interrupt had arrived. |
0x00000280, 284, 290 | Status Clear Registers 0, 1, 4 | An array of five registers that provide status on the interrupts managed by the INTD. Registers 2 and 3 are not used in the QMSS INTD. Registers 0, 1, and 4 expose one bit per QMSS interrupt (see each individual register layout). Reading the registers returns a 1 bit for each interrupt that has been triggered. Writing to the registers causes status bits to be cleared. Clearing status bits does not affect the count of interrupts in the Int Count Registers, nor does it clear the interrupt internally (the EOI register still needs to be written). In blocks where a single event can represent multiple grouped interrupts, these registers can be used to determine which interrupts have triggered. Because QMSS does not group interrupts, this is needed only to keep it clear which events have been processed. |
0x00000300 to 3C4 | Interrupt N Count Registers | An array of fifty registers, one per QMSS interrupt. Each register contains a count of the interrupts that have triggered and not processed. In QMSS, this count saturates at 3. Reading the register returns the count. Writing a non-zero value to the register subtracts that value from the count. Writing a 0 clears the count. |