SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History

C.1 KeyStone I Addresses:

#define QMSS_CFG_BASE (0x02a00000u) #define QMSS_VBUSM_BASE (0x34000000u) #define SRIO_CFG_BASE (0x02900000u) #define PASS_CFG_BASE (0x02000000u) #define FFTCA_CFG_BASE (0x021f0000u) #define FFTCB_CFG_BASE (0x021f4000u) #define AIF_CFG_BASE (0x01f00000u) /* Define QMSS Register block regions. */ #define QM_CTRL_REGION (QMSS_CFG_BASE + 0x00068000u) #define QM_DESC_REGION (QMSS_CFG_BASE + 0x0006a000u) #define QM_QMAN_REGION (QMSS_CFG_BASE + 0x00020000u) #define QM_QMAN_VBUSM_REGION (QMSS_VBUSM_BASE + 0x00020000u) #define QM_PEEK_REGION (QMSS_CFG_BASE + 0x00000000u) #define QM_LRAM_REGION ( + 0x00080000u) #define QM_INTD_REGION (QMSS_CFG_BASE + 0x000a0000u) #define QM_PROXY_REGION (QMSS_CFG_BASE + 0x00040000u) #define PDSP1_CMD_REGION (QMSS_CFG_BASE + 0x000b8000u) #define PDSP2_CMD_REGION (QMSS_CFG_BASE + 0x000bc000u) #define PDSP1_REG_REGION (QMSS_CFG_BASE + 0x0006E000u) #define PDSP2_REG_REGION (QMSS_CFG_BASE + 0x0006F000u) #define PDSP1_IRAM_REGION (QMSS_CFG_BASE + 0x00060000u) #define PDSP2_IRAM_REGION (QMSS_CFG_BASE + 0x00061000u) /* Define QMSS PKTDMA Register block regions. */ #define QMSS_PKTDMA_GBL_CFG_REGION (QMSS_CFG_BASE + 0x0006c000u) #define QMSS_PKTDMA_TX_CHAN_REGION (QMSS_CFG_BASE + 0x0006c400u) #define QMSS_PKTDMA_RX_CHAN_REGION (QMSS_CFG_BASE + 0x0006c800u) #define QMSS_PKTDMA_TX_SCHD_REGION (QMSS_CFG_BASE + 0x0006cc00u) #define QMSS_PKTDMA_RX_FLOW_REGION (QMSS_CFG_BASE + 0x0006d000u) /* Define PASS PKTDMA Register block regions. */ #define PASS_PKTDMA_GBL_CFG_REGION (PASS_CFG_BASE + 0x00004000u) #define PASS_PKTDMA_TX_CHAN_REGION (PASS_CFG_BASE + 0x00004400u) #define PASS_PKTDMA_RX_CHAN_REGION (PASS_CFG_BASE + 0x00004800u) #define PASS_PKTDMA_TX_SCHD_REGION (PASS_CFG_BASE + 0x00004c00u) #define PASS_PKTDMA_RX_FLOW_REGION (PASS_CFG_BASE + 0x00005000u) /* Define SRIO PKTDMA Register block regions. */ #define SRIO_PKTDMA_GBL_CFG_REGION (SRIO_CFG_BASE + 0x00001000u) #define SRIO_PKTDMA_TX_CHAN_REGION (SRIO_CFG_BASE + 0x00001400u) #define SRIO_PKTDMA_RX_CHAN_REGION (SRIO_CFG_BASE + 0x00001800u) #define SRIO_PKTDMA_TX_SCHD_REGION (SRIO_CFG_BASE + 0x00001c00u) #define SRIO_PKTDMA_RX_FLOW_REGION (SRIO_CFG_BASE + 0x00002000u) /* Define FFTC A PKTDMA Register block regions. */ #define FFTCA_PKTDMA_GBL_CFG_REGION (FFTCA_CFG_BASE + 0x00000200u) #define FFTCA_PKTDMA_TX_CHAN_REGION (FFTCA_CFG_BASE + 0x00000400u) #define FFTCA_PKTDMA_RX_CHAN_REGION (FFTCA_CFG_BASE + 0x00000500u) #define FFTCA_PKTDMA_TX_SCHD_REGION (FFTCA_CFG_BASE + 0x00000300u) #define FFTCA_PKTDMA_RX_FLOW_REGION (FFTCA_CFG_BASE + 0x00000600u) /* Define FFTC B PKTDMA Register block regions. */ #define FFTCB_PKTDMA_GBL_CFG_REGION (FFTCB_CFG_BASE + 0x00000200u) #define FFTCB_PKTDMA_TX_CHAN_REGION (FFTCB_CFG_BASE + 0x00000400u) #define FFTCB_PKTDMA_RX_CHAN_REGION (FFTCB_CFG_BASE + 0x00000500u) #define FFTCB_PKTDMA_TX_SCHD_REGION (FFTCB_CFG_BASE + 0x00000300u) #define FFTCB_PKTDMA_RX_FLOW_REGION (FFTCB_CFG_BASE + 0x00000600u) /* Define AIF PKTDMA Register block regions. */ #define AIF_PKTDMA_GBL_CFG_REGION (AIF_CFG_BASE + 0x00014000u) #define AIF_PKTDMA_TX_CHAN_REGION (AIF_CFG_BASE + 0x00016000u) #define AIF_PKTDMA_RX_CHAN_REGION (AIF_CFG_BASE + 0x00018000u) //#define AIF_PKTDMA_TX_SCHD_REGION (AIF_CFG_BASE + 0x00000000u) #define AIF_PKTDMA_RX_FLOW_REGION (AIF_CFG_BASE + 0x0001a000u) /********************************************************************** * Define offsets to individual QM registers within an address region. */ /* Queue Manager Region */ #define QM_REG_QUE_REVISION 0x000 #define QM_REG_QUE_DIVERSION 0x008 #define QM_REG_STARVATION_CNT 0x020 #define QM_REG_LINKRAM_0_BASE 0x00c #define QM_REG_LINKRAM_0_SIZE 0x010 #define QM_REG_LINKRAM_1_BASE 0x014 /* Descriptor Memory Region */ #define QM_REG_MEM_REGION_BASE 0x000 #define QM_REG_MEM_REGION_INDEX 0x004 #define QM_REG_MEM_REGION_SETUP 0x008 /* Queue Management Region */ #define QM_REG_QUE_REG_A 0x000 #define QM_REG_QUE_REG_B 0x004 #define QM_REG_QUE_REG_C 0x008 #define QM_REG_QUE_REG_D 0x00c /* Queue Status Region */ #define QM_REG_QUE_STATUS_REG_A 0x000 #define QM_REG_QUE_STATUS_REG_B 0x004 #define QM_REG_QUE_STATUS_REG_C 0x008 #define QM_REG_QUE_STATUS_REG_D 0x00c /* Interrupt Distributor (INTD) Region */ #define QM_REG_INTD_REVISION 0x000 #define QM_REG_INTD_EOI 0x010 #define QM_REG_INTD_STATUS 0x200 #define QM_REG_INTD_STATUS_CLEAR 0x280 #define QM_REG_INTD_INT_COUNT 0x300 /* PDSP(n) Reg Region */ #define QM_REG_PDSP_CONTROL 0x000 #define QM_REG_PDSP_STATUS 0x004 #define QM_REG_PDSP_CYCLE_COUNT 0x00c #define QM_REG_PDSP_STALL_COUNT 0x010 /********************************************************************** * Define offsets to individual PKTDMA registers within an address region. */ /* Global Cfg Register Block */ #define PKTDMA_REG_REVISION 0x000 #define PKTDMA_REG_PERFORMANCE_CTRL 0x004 #define PKTDMA_REG_EMULATION_CTRL 0x008 #define PKTDMA_REG_PRIORITY_CTRL 0x00c #define PKTDMA_REG_QM0_BASE_ADDR 0x010 #define PKTDMA_REG_QM1_BASE_ADDR 0x014 #define PKTDMA_REG_QM2_BASE_ADDR 0x018 #define PKTDMA_REG_QM3_BASE_ADDR 0x01c /* Tx Chan Cfg Register Block */ #define PKTDMA_REG_TX_CHAN_CFG_A 0x000 #define PKTDMA_REG_TX_CHAN_CFG_B 0x004 /* Rx Chan Cfg Register Block */ #define PKTDMA_REG_RX_CHAN_CFG_A 0x000 /* Rx Flow Cfg Register Block */ #define PKTDMA_REG_RX_FLOW_CFG_A 0x000 #define PKTDMA_REG_RX_FLOW_CFG_B 0x004 #define PKTDMA_REG_RX_FLOW_CFG_C 0x008 #define PKTDMA_REG_RX_FLOW_CFG_D 0x00c #define PKTDMA_REG_RX_FLOW_CFG_E 0x010 #define PKTDMA_REG_RX_FLOW_CFG_F 0x014 #define PKTDMA_REG_RX_FLOW_CFG_G 0x018 #define PKTDMA_REG_RX_FLOW_CFG_H 0x01c /* Tx Sched Cfg Register Block */ #define PKTDMA_REG_TX_SCHED_CHAN_CFG 0x000