SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
Table 5-7 shows the mapping of queues to high priority accumulation channels to DSP and function for TCI660x and C667x devices. Note that each queue and interrupt maps to a specific DSP core. Also, the queues shown are the suggested mapping. Other queues may be used.
DSP | Queue | High Priority Channel | Interrupt Name | DSP Event |
---|---|---|---|---|
core N
(N = 0 to 7) |
704 + N | N | qmss_intr1_0+N | 48 |
712 + N | N + 8 | qmss_intr1_8+N | 49 | |
720 + N | N + 16 | qmss_intr1_16+N | 50 | |
728 + N | N + 24 | qmss_intr1_24+N | 51 |
The mapping of low priority events is the same as shown in Table 5-5.
Table 5-8 shows the mapping of queues with queue pend signals tied to the chip-level CP-INTC0 and CP-INTC1 interrupt controllers.
Queue | Interrupt Name | CPINTC0 Input Event | CPINTC1 Input Event |
---|---|---|---|
652 | qm_int_pass_txq_pend_12 | 47 | |
653 | qm_int_pass_txq_pend_13 | 91 | |
654 | qm_int_pass_txq_pend_14 | 93 | |
655 | qm_int_pass_txq_pend_15 | 95 | |
656 | qm_int_pass_txq_pend_16 | 97 | |
657 | qm_int_pass_txq_pend_17 | 151 | |
658 | qm_int_pass_txq_pend_18 | 152 | 47 |
659 | qm_int_pass_txq_pend_19 | 153 | 91 |
660 | qm_int_pass_txq_pend_20 | 154 | 93 |
661 | qm_int_pass_txq_pend_21 | 155 | 95 |
662 | qm_int_pass_txq_pend_22 | 156 | 97 |
663 | qm_int_pass_txq_pend_23 | 157 | 151 |
664 | qm_int_pass_txq_pend_24 | 158 | 152 |
665 | qm_int_pass_txq_pend_25 | 159 | 153 |
666 | qm_int_pass_txq_pend_26 | 154 | |
667 | qm_int_pass_txq_pend_27 | 155 | |
668 | qm_int_pass_txq_pend_28 | 156 | |
669 | qm_int_pass_txq_pend_29 | 157 | |
670 | qm_int_pass_txq_pend_30 | 158 | |
671 | qm_int_pass_txq_pend_31 | 159 |