4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
The linking RAM Region 0 Base Address Register (Figure 4-3) is used to set the base address for the first portion of the linking RAM. This address must be 32-bit aligned.
Figure 4-3 Linking RAM Region 0 Base Address Register (0x0000000C)
Legend: R/W = Read/Write; - n = value after reset |
Table 4-4 Linking RAM Region 0 Base Address Register Field Descriptions
Bit |
Field |
Description |
31-0 |
REGION0_BASE |
This field stores the base address for the first region of the linking RAM. This may be anywhere in 32-bit address space but would be typically located in on-chip memory. To use the QMSS’ internal Linking RAM, specify a value of 0x00080000 for KeyStone I, 0x00100000 for KeyStone II’s QM1. Depending on the Shared/Split mode configuration, the value for QM2 will be 0x00100000 (Shared mode) or 0x00100000 +(8 * number_of_descriptors_in_QM1_split). |