SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The Linking RAM Region 0 Size Register (Figure 4-4) is used to set the size of the array of linking pointers that are located in region 0 of linking RAM. The value specified in this register defines the range of descriptor indexes in Linking RAM 0. Any descriptor index less than or equal to this value will be considered in Linking RAM 0. A descriptor index greater than this value will be in Linking RAM 1.
31 | 19 | 18 | 0 |
Reserved | REGION0_SIZE |
R-0 | R/W-0 |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-19 | Reserved | Reads return 0 and writes have no effect |
18-0 | REGION0_SIZE | This field indicates the number of entries that are contained in the linking RAM region 0. A descriptor with index less than or equal to region0_size value has its linking location in region 0.
KeyStone I: To specify the entire QMSS internal Linking RAM to be used for Linking RAM 0, use the value 0x3FFF. If no Linking RAM 1 is used, or if the total descriptors used is less than 16K, it is still safe to use 0x3FFF, because every descriptor index must be less than 16K (0x4000). KeyStone II: To specify the entire QMSS internal Linking RAM to be used for Linking RAM 0, use the value 0x7FFF. This creates a Shared mode configuration. For a Split mode configuration, first decide how many descriptors of the 32K will be used by each QM, then program those values minus 1. |