31-22 |
Reserved |
Reads return 0 and writes have no effect. |
21-16 |
WARB_FIFO_DEPTH |
This field sets the depth of the write arbitration FIFO, which stores write transaction information between the command arbiter and write data arbiters in the Bus Interface Unit. This value can be set to a range of 1 to 32. Setting this field to smaller values will prevent the PKTDMA from having an excess of write transactions outstanding whose data is still waiting to be transferred. System performance can suffer if write commands are allowed to be issued long before the corresponding write data will be transferred. This field allows the command count to be optimized based on system dynamics. |
15-0 |
TIMEOUT |
This field sets a timeout duration in clock cycles. It controls the minimum amount of time that an RX channel will be required to wait when it encounters a buffer starvation condition and the RX error handling bit is set to 1 (packet is to be preserved - no discard). If the RX error handling bit in the flow table is cleared, this field will have no effect on the RX operation. When this field is set to 0, the RX engine will not force an RX channel to wait after encountering a starvation event (the feature is disabled). When this field is set to a value other than 0, the RX engine will force any channel whose associated flow had the RX error handling bit asserted and which encounters starvation to wait for at least the specified # of clock cycles before coming into context again to retry the access to the QM. This is intended to control potentially debilitating effects on the QM performance that can be caused by the PKTDMA modules continually polling the QM. The exact number of clock cycles between QM access attempts is not important and will not be exact. The number of cycles waited will be at least as large as TIMEOUT. |