4.2.1.4 Priority Control Register (0x0C)
The Priority Control Register (Figure 4-22) is used to control the priority of the transactions that the DMA generates on its master (VBUSM) interface. They set sideband signals on the bus; they do not affect anything within the DMA.
Figure 4-22 Priority Control Register (0x0C)
Reserved |
RX_PRIORITY |
Reserved |
TX_PRIORITY |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Table 4-27 Priority Control Register Field Descriptions
Bit |
Field |
Description |
31-19 |
Reserved |
Reads return 0 and writes have no effect. |
18-16 |
RX_PRIORITY |
This field contains the 3-bit value that will be output on the mem_cpriority and mem_cepriority outputs during all RX transactions. |
31-19 |
Reserved |
Reads return 0 and writes have no effect. |
2-0 |
TX_PRIORITY |
This field contains the 3-bit value that will be output on the mem_cpriority and mem_cepriority outputs during all TX transactions. |