SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The PDSP control / status registers region contains registers for the PDSP. The control / status registers region is accessed using the Instruction RAM VBUSP slave interface and the PDSP_iram_regs_req input. The control / status registers region memory map is as follows:
Table 4-65 shows registers within each PDSP Register region.
Offset | Name | Description |
---|---|---|
0x00000000 | Control Register | The Control Register allows software to setup and enable the PDSP. |
0x00000004 | Status Register | The Status Register allows software to find (with a one-cycle delay) the PDSP’s Program Counter address. |
0x0000000c | Cycle Count Register | The Cycle Count Register counts the number of cycles for which the PDSP has been enabled. |
0x00000010 | Stall Count Registers | The Stall Count register counts the number of cycles for which the PDSP has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count. |