SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The QoS SRIO Queue Monitoring Record format is shown in Table 4-63:
QoS Queue Offset | Field | |||
---|---|---|---|---|
Byte 3 | Byte 2 | Byte 1 | Byte 0 | |
0x00 | Reserved | SRIO Queue Count | SRIO Queue Base | |
0x04 | Hardware TXQ 0 | Reserved | Threshold 0 | |
0x08 | Hardware TXQ 1 | Reserved | Threshold 1 | |
0x0C | Hardware TXQ 2 | Reserved | Threshold 2 | |
0x10 | Hardware TXQ 3 | Reserved | Threshold 3 | |
0x14 | Hardware TXQ 4 | Reserved | Threshold 4 |
Table 4-64 shows the breakdown of each field:
Field | Byte Width | Notes |
---|---|---|
SRIO Queue Base | 2 | The Queue index of the base queue of the SRIO queue cluster. This value must be a multiple of 32. |
SRIO Queue Count | 1 | The number of queues to monitor. This controls both the number of valid TXQ entries in this structure, plus the number of queues considered valid from the SRIO base queue index. |
Threshold N | 1 | This is the high water mark for SRIO Queue Set N at which point additional transmit packets will not be accepted. |
Hardware TXQ N | 2 | This is the actual hardware queue onto which transmit packets must be eventually placed for Queue Set N. |