SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The RX Flow N Configuration Register G contains static configuration information for the RX DMA flow. The fields in this register can be safely changed only when all of the DMA channels that use this flow have been disabled. This register is optional. The fields in this register are shown in Figure 4-33:
31 | 16 | 15 | 14 | 13 | 12 | 11 | 0 |
RX_SIZE_THRESH2 | Reserved | RX_FDQ0_SZ1_QMGR | RX_FDQ0_SZ1_QNUM |
W-0 | R-0 | W-0 | W-0 |
Legend: R = Read only; W = Write only; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-16 | RX_SIZE_THRESH2 | RX packet size threshold 2. This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the RX_FDQ0_SZ2_QMGR and RX_FDQ0_SZ2_QNUM fields.
If enabled, this value must be greater than the value given in the rx_size_thresh1 field. This field is optional. |
15-14 | Reserved | Reads return 0 and writes have no effect. |
13-12 | RX_FDQ0_SZ1_QMGR | RX free descriptor 0 queue manager index – size 1: This field specifies which queue manager should be used for the 1st RX buffer in a packet whose size is less than or equal to the RX_SIZE0 value. This field is optional. |
11-0 | RX_FDQ0_SZ1_QNUM | RX free descriptor 0 queue index – size 1: This field specifies which free descriptor queue should be used for the 1st RX buffer in a packet whose size is less than or equal to the RX_SIZE0 value. This field is optional. |