4.4.1.10 Status Clear Register 4 (0x00000290)
Status Register 4 (Figure 4-49) provides status on the QMSS PKTDMA starvation interrupts managed by the INTD. Reading this register returns a 1 bit for each interrupt that has been triggered. Writing to the register causes status bits to be cleared. Clearing status bits does not affect the count of interrupts in the Int Count Registers, nor does it clear the interrupt internally (the EOI register still needs to be written). In blocks where a single event can represent multiple grouped interrupts, these registers can be used to determine which interrupts have triggered. Because the QMSS does not group interrupts, this is needed only to keep clear which events have been processed (it is optional).
Figure 4-49 Status Clear Register 4 (0x00000290)
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Table 4-80 Status Clear Register 4 Field Descriptions
Bit |
Field |
Description |
31-2 |
Reserved |
Reads return 0 and writes have no effect |
1 |
INT1 |
PKTDMA Starvation Interrupt 1 status. This clears the status of RX MOP starvation (available only for host-type packets). |
0 |
INT0 |
PKTDMA Starvation Interrupt 0 status. This clears the status of RX SOP starvation. |