SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
Status Register 1 (Figure 4-43) provides status on the Low Priority Accumulator Interrupts managed by INTD. Reading this register returns a 1 bit for each interrupt that has been triggered. Writing to the register causes an interrupt to be triggered for each set 1 bit just as if the corresponding input interrupt had arrived.
31 | 16 | 15 | 14 | ... | 1 | 0 |
Reserved | INT15 | INT14 – INT1 | INT0 |
R-0 | R/W-0 | R/W-0 | R/W-0 |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-16 | Reserved | Reads return 0 and writes have no effect |
15 | INT15 | Low Priority Accumulator Interrupt 15 status |
14
... 1 |
INT14 ...
INT1 |
Low Priority Accumulator Interrupt n status |
0 | INT0 | Low Priority Accumulator Interrupt 0 status |