4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
The TX Channel Configuration Register A (Figure 4-24) contains real-time control and status information for the TX DMA channel. The fields in this register can safely be changed while the channel is in operation.
Figure 4-24 TX Channel N Global Configuration Register A (0x000 + 32×N)
TX_ENABLE |
TX_TEARDOWN |
TX_PAUSE |
Reserved |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Table 4-30 TX Channel N Global Configuration Register A Field Descriptions
Bit |
Field |
Description |
31 |
TX_ENABLE |
This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the attached application block and data loss. This field is encoded as follows:
- 0 = channel is disabled
- 1 = channel is enabled
This field will be cleared after a channel teardown is complete.
|
30 |
TX_TEARDOWN |
Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete. |
29 |
TX_PAUSE |
Setting this bit will cause the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow. |
28-0 |
Reserved |
Reads return 0 and writes have no effect. |