SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The TX Channel N Scheduler Configuration Register contains static configuration information that affects the conditions under which each channel will be given an opportunity to use the TX DMA unit(s). The fields in this register are shown in Figure 4-35:
31 | 2 | 1 | 0 |
Reserved | PRIORITY |
R-0 | R/W-0 |
Legend: R = Read only; R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-2 | Reserved | Reads return 0 and writes have no effect. |
1-0 | PRIORITY | TX scheduling priority. These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the TX DMA units. This field is encoded as follows:
Arbitration between bins is performed in a strict priority fashion. High priority channels will always be serviced first. If no high priority channels are requesting then all medium-high priority channels will be serviced next. If no high priority or medium-high priority channels are requesting then all medium-low priority channels will be serviced next. When no other channels are requesting, the low priority channels will be serviced. All channels within a given bin are serviced in a round robin order. Only channels that are enabled and that have sufficient free space in their per channel FIFO will be included in the round robin arbitration. |