SPRUHJ1 User guide

SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

9.3 Decimating in Hardware

The highlighted tick rate shown in Figure 10-34 is used to decimate the execution of InstaSPIN in hardware.

Figure 9-34 Hardware Decimation Software Execution Clock Tree

The only decimation in hardware possible is to trigger the conversions of the ADC at a different rate, other than every PWM cycle. The following configuration in file <user.h>:

//! \brief Defines the number of pwm clock ticks per isr clock tick
//!        Note: Valid values are 1, 2 or 3 only
#define USER_NUM_PWM_TICKS_PER_ISR_TICK        (1)

With the above example, a start of conversion (SOC) event is triggered every single PWM period, leading to Figure 10-35.

Figure 9-35 SOC Event Timing

Figure 10-36 represents the values of this timing diagram in highlighted boxes.

Figure 9-36 SOC Event Software Execution Clock Tree

If a requirement to have a higher PWM frequency in the application, a way of doing this in hardware is by triggering conversions every second or every third PWM cycle. The following example shows how to configure the PWM to trigger conversions on every second PWM cycle:

//! \brief Defines the number of pwm clock ticks per isr clock tick
//!        Note: Valid values are 1, 2 or 3 only
#define USER_NUM_PWM_TICKS_PER_ISR_TICK        (2)

Figure 10-37 shows the respective timing diagram.

Figure 9-37 PWM Conversions on Every Second PWM Cycle Timing

Figure 10-38 represents the values of this timing diagram in highlighted boxes.

Figure 9-38 PWM Conversions on Every Second PWM Cycle Software Execution Clock Tree

If even higher frequency is required, the PWM module can also trigger conversions every third PWM cycles, configured as follows:

//! \brief Defines the number of pwm clock ticks per isr clock tick
//!        Note: Valid values are 1, 2 or 3 only
#define USER_NUM_PWM_TICKS_PER_ISR_TICK        (3)

Figure 10-39 shows the respective timing diagram.

Figure 9-39 PWM Conversions on Every Third PWM Cycle Timing

Figure 10-40 represents the values of this timing diagram in highlighted boxes. Notice how the interrupt period changes with respect to the PWM period. This allows a higher PWM frequency maintaining a higher interrupt period. A higher interrupt period allows InstaSPIN to execute in time, even though the PWM frequency is higher.

Figure 9-40 PWM Conversions on Every Third PWM Cycle Software Execution Clock Tree