SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
As soon as the controller is enabled, and full identification starts, the first task performed by the controller state machine is the offset calculation. This is denoted by the state of the controller state machine named: CTRL_State_OffLine. The estimator state stays in the idle state (EST_State_Idle) during the controller offline state.
The offsets calculation is done in order to set the zeros for current measurements and voltage measurements. In order to calculate the offsets, a 50% duty cycle is set on the EPWM pins for a pre-configured period of time. The time in which these offsets are calculated can be changed by the user, and it is configured in user.c file as shown below:
pUserParams->ctrlWaitTime[CTRL_State_OffLine]=(uint_least32_t)(5.0*USER_CTRL_FREQ_Hz);
In the example above, the offsets calibration is done for a period of 5 seconds. Although 5 seconds for offset calibration is enough for most of the hardware, if the user requires a shorter or longer time for their particular needs, simply change the 5.0 value of the line of code above, and the time to do offset calibration will change according to the new setting.
Once the offset calibration is done, the final result will be stored in the driver object (HAL_Obj). For more details about HAL_Obj, see Section 4. Figure 7-9 shows the final results of calibrating the offsets for the DRV8312 Revision D board.
The current offsets, also known as bias values, ideally should be:
Note: for definitions of the variables used in the following equations, see Section 5.1.
This current scale factor (Current_sf or USER_CURRENT_SF) is calculated in the following example with values for the DRV8312 board revision D:
The 0.5 value comes from the fact that the current feedback circuit is bidirectional, providing an ideal zero at VDD/2, or 1.65V.
The voltage bias is calculated as follows. First, the voltage scale factor is done as shown here:
The ideal voltage bias is based on the fact that when introducing a 50% duty cycle to measure these offsets, the phase voltage will present a voltage close to VBUS * 50%, and then this is scaled down depending on the maximum voltage measured by the ADC. Considering a DRV8312 revision D board with a VBUS of 24V, the ideal voltage bias results in 0.25, as shown below:
In the oscilloscope plot shown in Figure 7-10, the 50% duty cycle is shown, as well as the cursors measuring the 5 second period to do the offset calibration. On the left plot, no PWM can be seen due to the resolution of the horizontal scaling. On the left side, 1.65 V of amplitude is shown, which represents a 50% duty cycle of a 3.3 V signal. On the right side, the actual PWM signal is shown zoomed in to 50 µs per division.