SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 23-56 lists the memory-mapped registers for the EMIF2_CONFIG_REGS registers. All register offset addresses not listed in Table 23-56 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | EMIF2LOCK | EMIF2 Config Lock Register | Go | |
2h | EMIF2COMMIT | EMIF2 Config Lock Commit Register | EALLOW | Go |
8h | EMIF2ACCPROT0 | EMIF2 Config Register 0 | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 23-57 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
EMIF2LOCK is shown in Figure 23-41 and described in Table 23-58.
Return to the Summary Table.
EMIF2 Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_EMIF2 | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | LOCK_EMIF2 | R/W | 0h | Locks the write to access protection fields for EMIF2: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: CPU1.SYSRSn |
EMIF2COMMIT is shown in Figure 23-42 and described in Table 23-59.
Return to the Summary Table.
EMIF2 Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_EMIF2 | ||||||
R-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | COMMIT_EMIF2 | R/WSonce | 0h | Permanently Locks the write to access protection fields for EMIF2: 0: Write to ACCPROT fields are allowed based on value of lock field in EMIF2LOCK register. 1: Write to ACCPROT fields are permanently blocked. Reset type: CPU1.SYSRSn |
EMIF2ACCPROT0 is shown in Figure 23-43 and described in Table 23-60.
Return to the Summary Table.
EMIF2 Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_EMIF2 | FETCHPROT_EMIF2 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_EMIF2 | R/W | 0h | CPU WR Protection For EMIF2: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_EMIF2 | R/W | 0h | Fetch Protection For EMIF2 0: CPU Fetches are allowed. 1: CPU Fetches are blocked. Reset type: SYSRSn |