SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The USB transmit control and status endpoint n low 8-bit registers (USBTXCSRL[n]) provide control and status bits for transfers through the currently selected transmit endpoint.
Mode(s): | Host | Device |
The USBTXCSRL[n] registers in Host Mode are shown in Figure 22-41 and described in Table 22-43.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAKTO | CLRDT | STALLED | SETUP | FLUSH | ERROR | FIFONE | TXRDY |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | NAKTO | NAK Timeout. Software must clear this bit to allow the endpoint to continue. | |
0 | No timeout | ||
1 | Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register. | ||
6 | CLRDT | Clear DataToggle | |
0 | No effect | ||
1 | Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register. | ||
5 | STALLED | Endpoint Stalled. Software must clear this bit. | |
0 | A STALL handshake has not been received | ||
1 | Indicates that a STALL handshake has been received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. | ||
4 | SETUP | Setup Packet. | |
0 | No SETUP token is sent. | ||
1 | Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. | ||
Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register. | |||
3 | FLUSH | Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. | |
0 | No effect | ||
1 | Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. | ||
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. | |||
2 | ERROR | Error. Software must clear this bit. | |
0 | No error | ||
1 | Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in this situation. | ||
Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. | |||
1 | FIFONE | FIFO Not Empty | |
0 | The FIFO is empty | ||
1 | At least one packet is in the transmit FIFO. | ||
0 | TXRDY | Transmit Packet Ready. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. | |
0 | No transmit packet is ready. | ||
1 | Software sets this bit after loading a data packet into the TX FIFO. |
The USBTXCSRL[n] registers in Device Mode are shown in Figure 22-42 and described in Table 22-44.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CLRDT | STALLED | STALL | FLUSH | UNDRN | FIFONE | TXRDY |
R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | Reserved | 0 | Reserved |
6 | CLRDT | Clear Data Toggle | |
0 | No effect | ||
1 | Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register. | ||
5 | STALLED | Endpoint Stalled. Software must clear this bit. | |
0 | A STALL handshake has not been transmitted. | ||
1 | A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared. | ||
4 | STALL | Send Stall. Software clears this bit to terminate the STALL condition. | |
0 | No effect | ||
1 | Issues a STALL handshake to an IN token. | ||
3 | FLUSH | Flush FIFO. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. | |
0 | No effect | ||
1 | Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. | ||
This bit is cleared automatically. | |||
2 | UNDRN | Underrun. Software must clear this bit. | |
0 | No underrun | ||
1 | An IN token has been received when TXRDY is not set. | ||
1 | FIFONE | FIFO Not Empty | |
0 | The FIFO is empty. | ||
1 | At least one packet is in the transmit FIFO. | ||
0 | TXRDY | Transmit Packet Ready. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. | |
0 | No transmit packet is ready. | ||
1 | Software sets this bit after loading a data packet into the TX FIFO. | ||
This bit is cleared by writing a 1 to the RXRDYC bit. |