SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
(USBTXIE), offset 0x006
The USB transmit interrupt enable 16-bit register (USBTXIE) provides interrupt enable bits for the interrupts in the USBTXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all interrupts are enabled.
Note:The EP0 bit is special in Host and Device modes. Both the control IN and control OUT endpoints are captured in the EP0 bit of the USBTXIE register.
Mode(s): | Host | Device |
USBTXIS is shown in Figure 22-8 and described in Table 22-10.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EP15 | EP14 | EP13 | EP12 | EP11 | EP10 | EP9 | EP8 |
R-0 | |||||||
EP7 | EP6 | EP5 | EP4 | EP3 | EP2 | EP1 | EP0 |
R-0 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | |||
Bit | Field | Value | Description |
---|---|---|---|
15 | EP15 | TX Endpoint 15 Interrupt Enable | |
0 | The EP15 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP15 bit in the USBTXIS register is set. | ||
14 | EP14 | TX Endpoint 14 Interrupt Enable | |
0 | The EP14 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP14 bit in the USBTXIS register is set. | ||
13 | EP13 | TX Endpoint 13 Interrupt Enable | |
0 | The EP13 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP13 bit in the USBTXIS register is set. | ||
12 | EP12 | TX Endpoint 12 Interrupt Enable | |
0 | The EP12 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP12 bit in the USBTXIS register is set. | ||
11 | EP11 | TX Endpoint 11 Interrupt Enable | |
0 | The EP11 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP11 bit in the USBTXIS register is set. | ||
10 | EP10 | TX Endpoint 10 Interrupt Enable | |
0 | The EP10 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP10 bit in the USBTXIS register is set. | ||
9 | EP9 | TX Endpoint 9 Interrupt Enable | |
0 | The EP9 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP9 bit in the USBTXIS register is set. | ||
8 | EP8 | TX Endpoint 8 Interrupt Enable | |
0 | The EP8 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP8 bit in the USBTXIS register is set. | ||
7 | EP7 | TX Endpoint 7 Interrupt Enable | |
0 | The EP7 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP7 bit in the USBTXIS register is set. | ||
6 | EP6 | TX Endpoint 6 Interrupt Enable | |
0 | The EP6 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP6 bit in the USBTXIS register is set. | ||
5 | EP5 | TX Endpoint 5 Interrupt Enable | |
0 | The EP5 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP5 bit in the USBTXIS register is set. | ||
4 | EP4 | TX Endpoint 4 Interrupt Enable | |
0 | The EP4 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP4 bit in the USBTXIS register is set. | ||
3 | EP3 | TX Endpoint 3 Interrupt Enable | |
0 | The EP3 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP3 bit in the USBTXIS register is set. | ||
2 | EP2 | TX Endpoint 2 Interrupt Enable | |
0 | The EP2 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP2 bit in the USBTXIS register is set. | ||
1 | EP1 | TX Endpoint 1 Interrupt Enable | |
0 | The EP1 transmit interrupt is suppressed and not sent to the interrupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP1 bit in the USBTXIS register is set. | ||
0 | EP0 | TX and RX Endpoint 0 Interrupt Enable | |
0 | The EP0 transmit and receive interrupt is suppressed and not sent to the interupt controller. | ||
1 | An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set. |