SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
Table 10-15 lists the memory-mapped registers for the ADC_RESULT_REGS registers. All register offset addresses not listed in Table 10-15 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | ADCRESULT0 | ADC Result 0 Register | Go | |
1h | ADCRESULT1 | ADC Result 1 Register | Go | |
2h | ADCRESULT2 | ADC Result 2 Register | Go | |
3h | ADCRESULT3 | ADC Result 3 Register | Go | |
4h | ADCRESULT4 | ADC Result 4 Register | Go | |
5h | ADCRESULT5 | ADC Result 5 Register | Go | |
6h | ADCRESULT6 | ADC Result 6 Register | Go | |
7h | ADCRESULT7 | ADC Result 7 Register | Go | |
8h | ADCRESULT8 | ADC Result 8 Register | Go | |
9h | ADCRESULT9 | ADC Result 9 Register | Go | |
Ah | ADCRESULT10 | ADC Result 10 Register | Go | |
Bh | ADCRESULT11 | ADC Result 11 Register | Go | |
Ch | ADCRESULT12 | ADC Result 12 Register | Go | |
Dh | ADCRESULT13 | ADC Result 13 Register | Go | |
Eh | ADCRESULT14 | ADC Result 14 Register | Go | |
Fh | ADCRESULT15 | ADC Result 15 Register | Go | |
10h | ADCPPB1RESULT | ADC Post Processing Block 1 Result Register | Go | |
12h | ADCPPB2RESULT | ADC Post Processing Block 2 Result Register | Go | |
14h | ADCPPB3RESULT | ADC Post Processing Block 3 Result Register | Go | |
16h | ADCPPB4RESULT | ADC Post Processing Block 4 Result Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 10-16 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
ADCRESULT0 is shown in Figure 10-26 and described in Table 10-17.
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ADC Result 0 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT1 is shown in Figure 10-27 and described in Table 10-18.
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ADC Result 1 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT2 is shown in Figure 10-28 and described in Table 10-19.
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ADC Result 2 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT3 is shown in Figure 10-29 and described in Table 10-20.
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ADC Result 3 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT4 is shown in Figure 10-30 and described in Table 10-21.
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ADC Result 4 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT5 is shown in Figure 10-31 and described in Table 10-22.
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ADC Result 5 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT6 is shown in Figure 10-32 and described in Table 10-23.
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ADC Result 6 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT7 is shown in Figure 10-33 and described in Table 10-24.
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ADC Result 7 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT8 is shown in Figure 10-34 and described in Table 10-25.
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ADC Result 8 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT9 is shown in Figure 10-35 and described in Table 10-26.
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ADC Result 9 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT10 is shown in Figure 10-36 and described in Table 10-27.
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ADC Result 10 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT11 is shown in Figure 10-37 and described in Table 10-28.
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ADC Result 11 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT12 is shown in Figure 10-38 and described in Table 10-29.
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ADC Result 12 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT13 is shown in Figure 10-39 and described in Table 10-30.
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ADC Result 13 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT14 is shown in Figure 10-40 and described in Table 10-31.
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ADC Result 14 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCRESULT15 is shown in Figure 10-41 and described in Table 10-32.
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ADC Result 15 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESULT | R | 0h | ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15, the digital result is placed in this bit field. Reset type: SYSRSn |
ADCPPB1RESULT is shown in Figure 10-42 and described in Table 10-33.
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ADC Post Processing Block 1 Result Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGN | PPBRESULT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the SIGN bits extend down to bit 12, and all reflect the same value as bit 12. Reset type: SYSRSn |
15-0 | PPBRESULT | R | 0h | ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available. If ADCINTFLG is polled to determine when to read the PPBRESULT, it may be necessary to add a NOP instruction to ensure that the updated post conversion processing result has posted to the register. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the PPBRESULT bits are limited to bits 12:0. Reset type: SYSRSn |
ADCPPB2RESULT is shown in Figure 10-43 and described in Table 10-34.
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ADC Post Processing Block 2 Result Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGN | PPBRESULT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the SIGN bits extend down to bit 12, and all reflect the same value as bit 12. Reset type: SYSRSn |
15-0 | PPBRESULT | R | 0h | ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available. If ADCINTFLG is polled to determine when to read the PPBRESULT, it may be necessary to add a NOP instruction to ensure that the updated post conversion processing result has posted to the register. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the PPBRESULT bits are limited to bits 12:0. Reset type: SYSRSn |
ADCPPB3RESULT is shown in Figure 10-44 and described in Table 10-35.
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ADC Post Processing Block 3 Result Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGN | PPBRESULT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the SIGN bits extend down to bit 12, and all reflect the same value as bit 12. Reset type: SYSRSn |
15-0 | PPBRESULT | R | 0h | ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available. If ADCINTFLG is polled to determine when to read the PPBRESULT, it may be necessary to add a NOP instruction to ensure that the updated post conversion processing result has posted to the register. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the PPBRESULT bits are limited to bits 12:0. Reset type: SYSRSn |
ADCPPB4RESULT is shown in Figure 10-45 and described in Table 10-36.
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ADC Post Processing Block 4 Result Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGN | PPBRESULT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the SIGN bits extend down to bit 12, and all reflect the same value as bit 12. Reset type: SYSRSn |
15-0 | PPBRESULT | R | 0h | ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available. If ADCINTFLG is polled to determine when to read the PPBRESULT, it may be necessary to add a NOP instruction to ensure that the updated post conversion processing result has posted to the register. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the PPBRESULT bits are limited to bits 12:0. Reset type: SYSRSn |