SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
Table 3-82 lists the memory-mapped registers for the SYNC_SOC_REGS registers. All register offset addresses not listed in Table 3-82 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | SYNCSELECT | Sync Input and Output Select Register | EALLOW | Go |
2h | ADCSOCOUTSELECT | External ADC (Off Chip) SOC Select Register | EALLOW | Go |
4h | SYNCSOCLOCK | SYNCSEL and EXTADCSOC Select Lock register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-83 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SYNCSELECT is shown in Figure 3-76 and described in Table 3-84.
Return to the Summary Table.
Sync Input and Output Select Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SYNCOUT | RESERVED | |||||
R-0-0h | R/W-0h | R-0-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ECAP4SYNCIN | ECAP1SYNCIN | EPWM10SYNCIN | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM10SYNCIN | EPWM7SYNCIN | EPWM4SYNCIN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R-0 | 0h | Reserved |
28-27 | SYNCOUT | R/W | 0h | Select Syncout Source: 00: EPWM1SYNCOUT selected 01: EPWM4SYNCOUT selected 10: EPWM7SYNCOUT selected 11: EPWM10SYNCOUT selected Reset type: CPU1.SYSRSn |
26-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14-12 | ECAP4SYNCIN | R/W | 0h | Selects Sync Input Source for ECAP4: 000: EPWM1SYNCOUT selected 001: EPWM4SYNCOUT selected 010: EPWM7SYNCOUT selected 011: EPWM10SYNCOUT selected 100: ECAP1SYNCOUT selected 101: EXTSYNCIN1 selected 110: EXTSYNCIN2 selected 111: Reserved Notes: [1] Reserved position defaults to 000 selection Reset type: CPU1.SYSRSn |
11-9 | ECAP1SYNCIN | R/W | 0h | Selects Sync Input Source for ECAP1: 000: EPWM1SYNCOUT selected 001: EPWM4SYNCOUT selected 010: EPWM7SYNCOUT selected 011: EPWM10SYNCOUT selected 100: ECAP1SYNCOUT selected (Reserved) 101: EXTSYNCIN1 selected 110: EXTSYNCIN2 selected 111: Reserved Notes: [1] Reserved position defaults to 000 selection Reset type: CPU1.SYSRSn |
8-6 | EPWM10SYNCIN | R/W | 0h | Selects Sync Input Source for EPWM10: 000: EPWM1SYNCOUT selected 001: EPWM4SYNCOUT selected 010: EPWM7SYNCOUT selected 011: EPWM10SYNCOUT selected (Reserved) 100: ECAP1SYNCOUT selected (Reserved) 101: EXTSYNCIN1 selected 110: EXTSYNCIN2 selected 111: Reserved Notes: [1] Reserved position defaults to 000 selection Reset type: CPU1.SYSRSn |
5-3 | EPWM7SYNCIN | R/W | 0h | Selects Sync Input Source for EPWM7: 000: EPWM1SYNCOUT selected 001: EPWM4SYNCOUT selected 010: EPWM7SYNCOUT selected (Reserved) 011: EPWM10SYNCOUT selected (Reserved) 100: ECAP1SYNCOUT selected (Reserved) 101: EXTSYNCIN1 selected 110: EXTSYNCIN2 selected 111: Reserved Notes: [1] Reserved position defaults to 000 selection Reset type: CPU1.SYSRSn |
2-0 | EPWM4SYNCIN | R/W | 0h | Selects Sync Input Source for EPWM4: 000: EPWM1SYNCOUT selected 001: EPWM4SYNCOUT selected (Reserved) 010: EPWM7SYNCOUT selected (Reserved) 011: EPWM10SYNCOUT selected (Reserved) 100: ECAP1SYNCOUT selected (Reserved) 101: EXTSYNCIN1 selected 110: EXTSYNCIN2 selected 111: Reserved Notes: [1] Reserved position defaults to 000 selection Reset type: CPU1.SYSRSn |
ADCSOCOUTSELECT is shown in Figure 3-77 and described in Table 3-85.
Return to the Summary Table.
The ADCSOCAO and ADCSOCBO signals will be active low for 32 SYSCLK cycles. They can be used to trigger a conversion on an external ADC.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PWM12SOCBEN | PWM11SOCBEN | PWM10SOCBEN | PWM9SOCBEN | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PWM8SOCBEN | PWM7SOCBEN | PWM6SOCBEN | PWM5SOCBEN | PWM4SOCBEN | PWM3SOCBEN | PWM2SOCBEN | PWM1SOCBEN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PWM12SOCAEN | PWM11SOCAEN | PWM10SOCAEN | PWM9SOCAEN | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM8SOCAEN | PWM7SOCAEN | PWM6SOCAEN | PWM5SOCAEN | PWM4SOCAEN | PWM3SOCAEN | PWM2SOCAEN | PWM1SOCAEN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R-0 | 0h | Reserved |
27 | PWM12SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
26 | PWM11SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
25 | PWM10SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
24 | PWM9SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
23 | PWM8SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
22 | PWM7SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
21 | PWM6SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
20 | PWM5SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
19 | PWM4SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
18 | PWM3SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
17 | PWM2SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
16 | PWM1SOCBEN | R/W | 0h | ADCSOCBO source select: 0: Respective EPWM SOCB output is not selected 1: Respective EPWM SOCB output is selected Reset type: CPU1.SYSRSn |
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | PWM12SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
10 | PWM11SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
9 | PWM10SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
8 | PWM9SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
7 | PWM8SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
6 | PWM7SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
5 | PWM6SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
4 | PWM5SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
3 | PWM4SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
2 | PWM3SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
1 | PWM2SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
0 | PWM1SOCAEN | R/W | 0h | ADCSOCAO source select: 0: Respective EPWM SOCA output is not selected 1: Respective EPWM SOCA output is selected Reset type: CPU1.SYSRSn |
SYNCSOCLOCK is shown in Figure 3-78 and described in Table 3-86.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCSOCOUTSELECT | SYNCSELECT | |||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | ADCSOCOUTSELECT | R/WSonce | 0h | ADCSOCOUTSELECT Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be creaed through a CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn |
0 | SYNCSELECT | R/WSonce | 0h | SYNCSELECT Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any bit in this register, once set can only be creaed through a CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: CPU1.SYSRSn |