SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
Table 8-23 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses not listed in Table 8-23 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | XBARFLG1 | X-Bar Input Flag Register 1 | Go | |
2h | XBARFLG2 | X-Bar Input Flag Register 2 | Go | |
4h | XBARFLG3 | X-Bar Input Flag Register 3 | Go | |
8h | XBARCLR1 | X-Bar Input Flag Clear Register 1 | Go | |
Ah | XBARCLR2 | X-Bar Input Flag Clear Register 2 | Go | |
Ch | XBARCLR3 | X-Bar Input Flag Clear Register 3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-24 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
XBARFLG1 is shown in Figure 8-22 and described in Table 8-25.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMPSS8_CTRIPOUTH | CMPSS8_CTRIPOUTL | CMPSS7_CTRIPOUTH | CMPSS7_CTRIPOUTL | CMPSS6_CTRIPOUTH | CMPSS6_CTRIPOUTL | CMPSS5_CTRIPOUTH | CMPSS5_CTRIPOUTL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPSS8_CTRIPH | CMPSS8_CTRIPL | CMPSS7_CTRIPH | CMPSS7_CTRIPL | CMPSS6_CTRIPH | CMPSS6_CTRIPL | CMPSS5_CTRIPH | CMPSS5_CTRIPL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CMPSS8_CTRIPOUTH | R | 0h | CMPSS8_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
30 | CMPSS8_CTRIPOUTL | R | 0h | CMPSS8_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
29 | CMPSS7_CTRIPOUTH | R | 0h | CMPSS7_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
28 | CMPSS7_CTRIPOUTL | R | 0h | CMPSS7_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
27 | CMPSS6_CTRIPOUTH | R | 0h | CMPSS6_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
26 | CMPSS6_CTRIPOUTL | R | 0h | CMPSS6_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
25 | CMPSS5_CTRIPOUTH | R | 0h | CMPSS5_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
24 | CMPSS5_CTRIPOUTL | R | 0h | CMPSS5_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
23 | CMPSS4_CTRIPOUTH | R | 0h | CMPSS4_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R | 0h | CMPSS4_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R | 0h | CMPSS3_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R | 0h | CMPSS3_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R | 0h | CMPSS2_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R | 0h | CMPSS2_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R | 0h | CMPSS1_CTRIPOUTH X-BAR Flag Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R | 0h | CMPSS1_CTRIPOUTL X-BAR Flag Reset type: CPU1.SYSRSn |
15 | CMPSS8_CTRIPH | R | 0h | CMPSS8_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
14 | CMPSS8_CTRIPL | R | 0h | CMPSS8_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
13 | CMPSS7_CTRIPH | R | 0h | CMPSS7_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
12 | CMPSS7_CTRIPL | R | 0h | CMPSS7_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
11 | CMPSS6_CTRIPH | R | 0h | CMPSS6_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
10 | CMPSS6_CTRIPL | R | 0h | CMPSS6_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
9 | CMPSS5_CTRIPH | R | 0h | CMPSS5_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
8 | CMPSS5_CTRIPL | R | 0h | CMPSS5_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
7 | CMPSS4_CTRIPH | R | 0h | CMPSS4_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R | 0h | CMPSS4_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R | 0h | CMPSS3_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R | 0h | CMPSS3_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R | 0h | CMPSS2_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R | 0h | CMPSS2_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R | 0h | CMPSS1_CTRIPH X-BAR Flag Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R | 0h | CMPSS1_CTRIPL X-BAR Flag Reset type: CPU1.SYSRSn |
XBARFLG2 is shown in Figure 8-23 and described in Table 8-26.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | ADCBEVT4 | ADCBEVT3 | ADCBEVT2 | ADCBEVT1 | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | ECAP6_OUT | ECAP5_OUT | ECAP4_OUT | ECAP3_OUT | ECAP2_OUT | ECAP1_OUT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLB4_OUT5 | CLB4_OUT4 | CLB3_OUT5 | CLB3_OUT4 | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCBO | ADCSOCAO | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R | 0h | ADCCEVT1 X-BAR Flag Reset type: CPU1.SYSRSn |
30 | ADCBEVT4 | R | 0h | ADCBEVT4 X-BAR Flag Reset type: CPU1.SYSRSn |
29 | ADCBEVT3 | R | 0h | ADCBEVT3 X-BAR Flag Reset type: CPU1.SYSRSn |
28 | ADCBEVT2 | R | 0h | ADCBEVT2 X-BAR Flag Reset type: CPU1.SYSRSn |
27 | ADCBEVT1 | R | 0h | ADCBEVT1 X-BAR Flag Reset type: CPU1.SYSRSn |
26 | ADCAEVT4 | R | 0h | ADCAEVT4 X-BAR Flag Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R | 0h | ADCAEVT3 X-BAR Flag Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R | 0h | ADCAEVT2 X-BAR Flag Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R | 0h | ADCAEVT1 X-BAR Flag Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R | 0h | EXTSYNCOUT X-BAR Flag Reset type: CPU1.SYSRSn |
21 | ECAP6_OUT | R | 0h | ECAP6_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
20 | ECAP5_OUT | R | 0h | ECAP5_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
19 | ECAP4_OUT | R | 0h | ECAP4_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
18 | ECAP3_OUT | R | 0h | ECAP3_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
17 | ECAP2_OUT | R | 0h | ECAP2_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R | 0h | ECAP1_OUT X-BAR Flag Reset type: CPU1.SYSRSn |
15 | CLB4_OUT5 | R | 0h | CLB4_OUT5 X-BAR Flag Reset type: CPU1.SYSRSn |
14 | CLB4_OUT4 | R | 0h | CLB4_OUT4 X-BAR Flag Reset type: CPU1.SYSRSn |
13 | CLB3_OUT5 | R | 0h | CLB3_OUT5 X-BAR Flag Reset type: CPU1.SYSRSn |
12 | CLB3_OUT4 | R | 0h | CLB3_OUT4 X-BAR Flag Reset type: CPU1.SYSRSn |
11 | CLB2_OUT5 | R | 0h | CLB2_OUT5 X-BAR Flag Reset type: CPU1.SYSRSn |
10 | CLB2_OUT4 | R | 0h | CLB2_OUT4 X-BAR Flag Reset type: CPU1.SYSRSn |
9 | CLB1_OUT5 | R | 0h | CLB1_OUT5 X-BAR Flag Reset type: CPU1.SYSRSn |
8 | CLB1_OUT4 | R | 0h | CLB1_OUT4 X-BAR Flag Reset type: CPU1.SYSRSn |
7 | ADCSOCBO | R | 0h | ADCSOCBO X-BAR Flag Reset type: CPU1.SYSRSn |
6 | ADCSOCAO | R | 0h | ADCSOCAO X-BAR Flag Reset type: CPU1.SYSRSn |
5 | INPUT6 | R | 0h | INPUT6 X-BAR Flag Reset type: CPU1.SYSRSn |
4 | INPUT5 | R | 0h | INPUT5 X-BAR Flag Reset type: CPU1.SYSRSn |
3 | INPUT4 | R | 0h | INPUT4 X-BAR Flag Reset type: CPU1.SYSRSn |
2 | INPUT3 | R | 0h | INPUT3 X-BAR Flag Reset type: CPU1.SYSRSn |
1 | INPUT2 | R | 0h | INPUT2 X-BAR Flag Reset type: CPU1.SYSRSn |
0 | INPUT1 | R | 0h | INPUT1 X-BAR Flag Reset type: CPU1.SYSRSn |
XBARFLG3 is shown in Figure 8-24 and described in Table 8-27.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SD2FLT4_COMPH | SD2FLT4_COMPL | SD2FLT3_COMPH | SD2FLT3_COMPL | SD2FLT2_COMPH | SD2FLT2_COMPL | SD2FLT1_COMPH |
R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SD2FLT1_COMPL | SD1FLT4_COMPH | SD1FLT4_COMPL | SD1FLT3_COMPH | SD1FLT3_COMPL | SD1FLT2_COMPH | SD1FLT2_COMPL | SD1FLT1_COMPH |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD1FLT1_COMPL | ADCDEVT4 | ADCDEVT3 | ADCDEVT2 | ADCDEVT1 | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R-0 | 0h | Reserved |
22 | SD2FLT4_COMPH | R | 0h | SD2FLT4_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
21 | SD2FLT4_COMPL | R | 0h | SD2FLT4_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
20 | SD2FLT3_COMPH | R | 0h | SD2FLT3_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
19 | SD2FLT3_COMPL | R | 0h | SD2FLT3_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
18 | SD2FLT2_COMPH | R | 0h | SD2FLT2_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
17 | SD2FLT2_COMPL | R | 0h | SD2FLT2_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
16 | SD2FLT1_COMPH | R | 0h | SD2FLT1_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
15 | SD2FLT1_COMPL | R | 0h | SD2FLT1_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
14 | SD1FLT4_COMPH | R | 0h | SD1FLT4_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
13 | SD1FLT4_COMPL | R | 0h | SD1FLT4_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
12 | SD1FLT3_COMPH | R | 0h | SD1FLT3_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
11 | SD1FLT3_COMPL | R | 0h | SD1FLT3_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
10 | SD1FLT2_COMPH | R | 0h | SD1FLT2_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
9 | SD1FLT2_COMPL | R | 0h | SD1FLT2_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
8 | SD1FLT1_COMPH | R | 0h | SD1FLT1_COMPH X-BAR Flag Reset type: CPU1.SYSRSn |
7 | SD1FLT1_COMPL | R | 0h | SD1FLT1_COMPL X-BAR Flag Reset type: CPU1.SYSRSn |
6 | ADCDEVT4 | R | 0h | ADCDEVT4 X-BAR Flag Reset type: CPU1.SYSRSn |
5 | ADCDEVT3 | R | 0h | ADCDEVT3 X-BAR Flag Reset type: CPU1.SYSRSn |
4 | ADCDEVT2 | R | 0h | ADCDEVT2 X-BAR Flag Reset type: CPU1.SYSRSn |
3 | ADCDEVT1 | R | 0h | ADCDEVT1 X-BAR Flag Reset type: CPU1.SYSRSn |
2 | ADCCEVT4 | R | 0h | ADCCEVT4 X-BAR Flag Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R | 0h | ADCCEVT3 X-BAR Flag Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R | 0h | ADCCEVT2 X-BAR Flag Reset type: CPU1.SYSRSn |
XBARCLR1 is shown in Figure 8-25 and described in Table 8-28.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG1 register.
1: Clears the corresponding bit in the XBARFLG1 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMPSS8_CTRIPOUTH | CMPSS8_CTRIPOUTL | CMPSS7_CTRIPOUTH | CMPSS7_CTRIPOUTL | CMPSS6_CTRIPOUTH | CMPSS6_CTRIPOUTL | CMPSS5_CTRIPOUTH | CMPSS5_CTRIPOUTL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPSS8_CTRIPH | CMPSS8_CTRIPL | CMPSS7_CTRIPH | CMPSS7_CTRIPL | CMPSS6_CTRIPH | CMPSS6_CTRIPL | CMPSS5_CTRIPH | CMPSS5_CTRIPL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CMPSS8_CTRIPOUTH | R-0/W1S | 0h | CMPSS8_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
30 | CMPSS8_CTRIPOUTL | R-0/W1S | 0h | CMPSS8_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
29 | CMPSS7_CTRIPOUTH | R-0/W1S | 0h | CMPSS7_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
28 | CMPSS7_CTRIPOUTL | R-0/W1S | 0h | CMPSS7_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
27 | CMPSS6_CTRIPOUTH | R-0/W1S | 0h | CMPSS6_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
26 | CMPSS6_CTRIPOUTL | R-0/W1S | 0h | CMPSS6_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
25 | CMPSS5_CTRIPOUTH | R-0/W1S | 0h | CMPSS5_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
24 | CMPSS5_CTRIPOUTL | R-0/W1S | 0h | CMPSS5_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
23 | CMPSS4_CTRIPOUTH | R-0/W1S | 0h | CMPSS4_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R-0/W1S | 0h | CMPSS4_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R-0/W1S | 0h | CMPSS3_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R-0/W1S | 0h | CMPSS3_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R-0/W1S | 0h | CMPSS2_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R-0/W1S | 0h | CMPSS2_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R-0/W1S | 0h | CMPSS1_CTRIPOUTH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R-0/W1S | 0h | CMPSS1_CTRIPOUTL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
15 | CMPSS8_CTRIPH | R-0/W1S | 0h | CMPSS8_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
14 | CMPSS8_CTRIPL | R-0/W1S | 0h | CMPSS8_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
13 | CMPSS7_CTRIPH | R-0/W1S | 0h | CMPSS7_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
12 | CMPSS7_CTRIPL | R-0/W1S | 0h | CMPSS7_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
11 | CMPSS6_CTRIPH | R-0/W1S | 0h | CMPSS6_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
10 | CMPSS6_CTRIPL | R-0/W1S | 0h | CMPSS6_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
9 | CMPSS5_CTRIPH | R-0/W1S | 0h | CMPSS5_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
8 | CMPSS5_CTRIPL | R-0/W1S | 0h | CMPSS5_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
7 | CMPSS4_CTRIPH | R-0/W1S | 0h | CMPSS4_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R-0/W1S | 0h | CMPSS4_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R-0/W1S | 0h | CMPSS3_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R-0/W1S | 0h | CMPSS3_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R-0/W1S | 0h | CMPSS2_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R-0/W1S | 0h | CMPSS2_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R-0/W1S | 0h | CMPSS1_CTRIPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R-0/W1S | 0h | CMPSS1_CTRIPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
XBARCLR2 is shown in Figure 8-26 and described in Table 8-29.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG2 register.
1: Clears the corresponding bit in the XBARFLG2 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | ADCBEVT4 | ADCBEVT3 | ADCBEVT2 | ADCBEVT1 | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | ECAP6_OUT | ECAP5_OUT | ECAP4_OUT | ECAP3_OUT | ECAP2_OUT | ECAP1_OUT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLB4_OUT5 | CLB4_OUT4 | CLB3_OUT5 | CLB3_OUT4 | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCBO | ADCSOCAO | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R-0/W1S | 0h | ADCCEVT1 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
30 | ADCBEVT4 | R-0/W1S | 0h | ADCBEVT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
29 | ADCBEVT3 | R-0/W1S | 0h | ADCBEVT3 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
28 | ADCBEVT2 | R-0/W1S | 0h | ADCBEVT2 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
27 | ADCBEVT1 | R-0/W1S | 0h | ADCBEVT1 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
26 | ADCAEVT4 | R-0/W1S | 0h | ADCAEVT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R-0/W1S | 0h | ADCAEVT3 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R-0/W1S | 0h | ADCAEVT2 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R-0/W1S | 0h | ADCAEVT1 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R-0/W1S | 0h | EXTSYNCOUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
21 | ECAP6_OUT | R-0/W1S | 0h | ECAP6_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
20 | ECAP5_OUT | R-0/W1S | 0h | ECAP5_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
19 | ECAP4_OUT | R-0/W1S | 0h | ECAP4_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
18 | ECAP3_OUT | R-0/W1S | 0h | ECAP3_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
17 | ECAP2_OUT | R-0/W1S | 0h | ECAP2_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R-0/W1S | 0h | ECAP1_OUT X-BAR Flag Clear Reset type: CPU1.SYSRSn |
15 | CLB4_OUT5 | R-0/W1S | 0h | CLB4_OUT5 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
14 | CLB4_OUT4 | R-0/W1S | 0h | CLB4_OUT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
13 | CLB3_OUT5 | R-0/W1S | 0h | CLB3_OUT5 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
12 | CLB3_OUT4 | R-0/W1S | 0h | CLB3_OUT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
11 | CLB2_OUT5 | R-0/W1S | 0h | CLB2_OUT5 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
10 | CLB2_OUT4 | R-0/W1S | 0h | CLB2_OUT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
9 | CLB1_OUT5 | R-0/W1S | 0h | CLB1_OUT5 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
8 | CLB1_OUT4 | R-0/W1S | 0h | CLB1_OUT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
7 | ADCSOCBO | R-0/W1S | 0h | ADCSOCBO X-BAR Flag Clear Reset type: CPU1.SYSRSn |
6 | ADCSOCAO | R-0/W1S | 0h | ADCSOCAO X-BAR Flag Clear Reset type: CPU1.SYSRSn |
5 | INPUT6 | R-0/W1S | 0h | INPUT6 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
4 | INPUT5 | R-0/W1S | 0h | INPUT5 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
3 | INPUT4 | R-0/W1S | 0h | INPUT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
2 | INPUT3 | R-0/W1S | 0h | INPUT3 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
1 | INPUT2 | R-0/W1S | 0h | INPUT2 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
0 | INPUT1 | R-0/W1S | 0h | INPUT1 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
XBARCLR3 is shown in Figure 8-27 and described in Table 8-30.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG3 register.
1: Clears the corresponding bit in the XBARFLG3 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SD2FLT4_COMPH | SD2FLT4_COMPL | SD2FLT3_COMPH | SD2FLT3_COMPL | SD2FLT2_COMPH | SD2FLT2_COMPL | SD2FLT1_COMPH |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SD2FLT1_COMPL | SD1FLT4_COMPH | SD1FLT4_COMPL | SD1FLT3_COMPH | SD1FLT3_COMPL | SD1FLT2_COMPH | SD1FLT2_COMPL | SD1FLT1_COMPH |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD1FLT1_COMPL | ADCDEVT4 | ADCDEVT3 | ADCDEVT2 | ADCDEVT1 | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R-0 | 0h | Reserved |
22 | SD2FLT4_COMPH | R-0/W1S | 0h | SD2FLT4_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
21 | SD2FLT4_COMPL | R-0/W1S | 0h | SD2FLT4_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
20 | SD2FLT3_COMPH | R-0/W1S | 0h | SD2FLT3_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
19 | SD2FLT3_COMPL | R-0/W1S | 0h | SD2FLT3_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
18 | SD2FLT2_COMPH | R-0/W1S | 0h | SD2FLT2_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
17 | SD2FLT2_COMPL | R-0/W1S | 0h | SD2FLT2_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
16 | SD2FLT1_COMPH | R-0/W1S | 0h | SD2FLT1_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
15 | SD2FLT1_COMPL | R-0/W1S | 0h | SD2FLT1_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
14 | SD1FLT4_COMPH | R-0/W1S | 0h | SD1FLT4_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
13 | SD1FLT4_COMPL | R-0/W1S | 0h | SD1FLT4_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
12 | SD1FLT3_COMPH | R-0/W1S | 0h | SD1FLT3_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
11 | SD1FLT3_COMPL | R-0/W1S | 0h | SD1FLT3_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
10 | SD1FLT2_COMPH | R-0/W1S | 0h | SD1FLT2_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
9 | SD1FLT2_COMPL | R-0/W1S | 0h | SD1FLT2_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
8 | SD1FLT1_COMPH | R-0/W1S | 0h | SD1FLT1_COMPH X-BAR Flag Clear Reset type: CPU1.SYSRSn |
7 | SD1FLT1_COMPL | R-0/W1S | 0h | SD1FLT1_COMPL X-BAR Flag Clear Reset type: CPU1.SYSRSn |
6 | ADCDEVT4 | R-0/W1S | 0h | ADCDEVT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
5 | ADCDEVT3 | R-0/W1S | 0h | ADCDEVT3 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
4 | ADCDEVT2 | R-0/W1S | 0h | ADCDEVT2 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
3 | ADCDEVT1 | R-0/W1S | 0h | ADCDEVT1 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
2 | ADCCEVT4 | R-0/W1S | 0h | ADCCEVT4 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R-0/W1S | 0h | ADCCEVT3 X-BAR Flag Clear Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R-0/W1S | 0h | ADCCEVT2 X-BAR Flag Clear Reset type: CPU1.SYSRSn |