SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
For correct operation, the input signal to the ADC must be allowed adequate time to charge the sample and hold capacitor, Ch. Typically, the S+H duration is chosen such that the sampling capacitor is charged to within ½ LSB or ¼ LSB of the final value, depending on the tolerable settling error.
The best methodology to determine the required settling time is to simulate the ADC and ADC driving circuits to make sure adequate settling performance. See ADC Input Circuit Evaluation for C2000 MCUs and Charge-Sharing Driving Circuits for C2000 ADCs for additional guidance on ADC signal conditioning circuit design and evaluation.
An approximation of the required settling time can also be determined using an RC settling model. The time constant for the model is given by the equation:
And the number of time constants needed is given by the equation:
So the total S+H time must be set to at least:
Where the following parameters are provided by the ADC input model in the device data sheet:
And the following parameters are dependent on the application design:
For example, assuming the following parameters:
The time constant is calculated as:
And the number of required time constants is:
So the S+H time must be set to at least: 37.8ns ˟ 7.13 = 270ns
If SYSCLK = 200MHz , then each SYSCLK cycle is 5ns. S+H duration is 270ns/5ns = 54 SYSCLK cycles, so ACQPS for this input is set to at least CEILING(54.0) – 1 = 53.
While this gives a rough estimate of the required acquisition window, a better method is to setup a circuit with the ADC input model, a model of the source impedance/capacitance, and any board parasitics in SPICE (or similar software) and simulate to verify that the sampling capacitor settles to the desired accuracy.