SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50 on the I2C-A bus as indicated in Figure 4-9. The EEPROM must adhere to conventional I2C EEPROM protocol, as described in this section, with a 16-bit base address architecture.
If the download is to be performed from a device other than an EEPROM, then that device must be set up to operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot function, the GPIO pins are configured for I2C-A operation and the I2C is initialized. The following requirements must be met when booting from the I2C module:
The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a 50 percent duty cycle at 100kHz bit rate (standard I2C mode) when the system clock is 10MHz. These registers can be modified after receiving the first few bytes from the EEPROM. This allows the communication to be increased up to a 400kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control the bus during this initialization phase. If the application requires another master during I2C boot mode, that master must be configured to hold off sending any I2C messages until the application software signals that the application software is past the bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an EEPROM is not present, the non-acknowledgment bit is not checked during the address phase of the data read messages (I2C_Get Word). If a non-acknowledgment is received during the data read messages, the I2C bus hangs. Table 14-41 shows the 8-bit data stream used by the I2C.
Byte | Contents | |
---|---|---|
1 | LSB: AA (KeyValue for memory width = 8 bits) | |
2 | MSB: 08h (KeyValue for memory width = 8 bits) | |
3 | LSB: I2CPSC[7:0] | |
4 | reserved | |
5 | LSB: I2CCLKH[7:0] | |
6 | MSB: I2CCLKH[15:8] | |
7 | LSB: I2CCLKL[7:0] | |
8 | MSB: I2CCLKL[15:8] | |
... ... |
... Data for this section. ... |
|
17 | LSB: Reserved for future use | |
18 | MSB: Reserved for future use | |
19 | LSB: Upper half of entry point PC | |
20 | MSB: Upper half of entry point PC[22:16] (Note: Always 0x00) | |
21 | LSB: Lower half of entry point PC[15:8] | |
22 | MSB: Lower half of entry point PC[7:0] | |
... ... |
... Data for this section. ... |
|
Blocks of data in the format size/destination address/data as shown in the generic data stream description. | ||
... ... |
... Data for this section. ... |
|
n | LSB: 00h | |
n+1 | MSB: 00h - indicates the end of the source |
The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 4-11 and Figure 4-12. The first communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue (0x08AA), is shown in Figure 4-11. All subsequent reads are shown in Figure 4-12 and are read two bytes at a time.