SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The USB transmit double packet buffer disable 16-bit register (USBTXDPKTBUFDIS) indicates which of the transmit endpoints have disabled the double-packet buffer functionality (see Double-Packet Buffering in Section 22.2.1.1.1).
Note: The USBTXDPKTBUFDIS register is not applicable to the control IN and control OUT endpoints, therefore the EP0 bit does not exist for the USBTXDPKTBUFDIS register.
Mode(s): | Host | Device |
USBTXDPKTBUFDIS is shown in Figure 22-57 and described in Table 22-61.
15 | 4 | 3 | 2 | 1 | 0 |
Reserved | EP3 | EP2 | EP1 | Rsvd |
R-0 | R/W-1 | R/W-1 | R/W-1 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
15-4 | Reserved | Reserved | |
3 | EP3 | EP3 RX Double-Packet Buffer Disable | |
0 | Disables double-packet buffering. | ||
1 | Enables double-packet buffering. | ||
2 | EP2 | EP2 RX Double-Packet Buffer Disable | |
0 | Disables double-packet buffering. | ||
1 | Enables double-packet buffering. | ||
1 | EP1 | EP1 RX Double-Packet Buffer Disable | |
0 | Disables double-packet buffering. | ||
1 | Enables double-packet buffering. | ||
0 | Reserved | 0 | Reserved |