SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
When the EMIF receives an SDRAM access request, the EMIF must convert the address of the access into the appropriate signals to send to the SDRAM device. The details of this address mapping are shown in Table 24-14 for 32-bit operation and in Table 24-15 for 16-bit operation. Using the settings of the IBANK and PAGESIZE fields of the SDRAM configuration register (SDRAM_CR), the EMIF determines which bits of the logical address are mapped to the SDRAM row, column, and bank addresses.
As the logical address is incremented by one halfword (16-bit operation), the column address is likewise incremented by one until a page boundary is reached. When the logical address increments across a page boundary, the EMIF moves into the same page in the next bank of the attached device by incrementing the bank address EM1BA and resetting the column address. The page in the previous bank is left open until necessary to close the page. This method of traversal through the SDRAM banks helps maximize the number of open banks inside of the SDRAM and results in an efficient use of the device. There is no limitation on the number of banks that can be open at one time, but only one page within a bank can be open at a time.
The EMIF uses the EM1DQM[3:0] pins during a WRT command to mask out selected bytes or entire words. The EM1DQM[3:0] pins are always low during a READ command.
IBANK | PAGESIZE | Logical Address | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31:27 | 26 | 25 | 24 | 23 | 22 | 21:14 | 13 | 12 | 11 | 10 | 9 | 8:1 | 0 | ||
0 | 0 | - | Row Address | Col Address | EM1DQM[2]/EM1DQM[3] | ||||||||||
1 | 0 | - | Row Address | EM1BA[0] | Col Address | EM1DQM[2]/EM1DQM[3] | |||||||||
2 | 0 | - | Row Address | EM1BA[1:0] | Col Address | EM1DQM[2]/EM1DQM[3] | |||||||||
0 | 1 | - | Row Address | Column Address | EM1DQM[2]/EM1DQM[3] | ||||||||||
1 | 1 | - | Row Address | EM1BA[0] | Column Address | EM1DQM[2]/EM1DQM[3] | |||||||||
2 | 1 | - | Row Address | EM1BA[1:0] | Column Address | EM1DQM[2]/EM1DQM[3] | |||||||||
0 | 2 | - | Row Address | Column Address | EM1DQM[2]/EM1DQM[3] | ||||||||||
1 | 2 | - | Row Address | EM1BA[0] | Column Address | EM1DQM[2]/EM1DQM[3] | |||||||||
2 | 2 | - | Row Address | EM1BA[1:0] | Column Address | EM1DQM[2]/EM1DQM[3] | |||||||||
0 | 3 | - | Row Address | Column Address | EM1DQM[2]/EM1DQM[3] | ||||||||||
1 | 3 | - | Row Address | EM1BA[0] | Column Address | EM1DQM[2]/EM1DQM[3] | |||||||||
2 | 3 | - | Row Address | EM1BA[1:0] | Column Address | EM1DQM[2]/EM1DQM[3] |
IBANK | PAGESIZE | Logical Address | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31:26 | 25 | 24 | 23 | 22 | 21 | 20:13 | 12 | 11 | 10 | 9 | 8 | 7:0 | ||
0 | 0 | - | Row Address | Col Address | ||||||||||
1 | 0 | - | Row Address | EM1BA[0] | Col Address | |||||||||
2 | 0 | - | Row Address | EM1BA[1:0] | Col Address | |||||||||
0 | 1 | - | Row Address | Column Address | ||||||||||
1 | 1 | - | Row Address | EM1BA[0] | Column Address | |||||||||
2 | 1 | - | Row Address | EM1BA[1:0] | Column Address | |||||||||
0 | 2 | - | Row Address | Column Address | ||||||||||
1 | 2 | - | Row Address | EM1BA[0] | Column Address | |||||||||
2 | 2 | - | Row Address | EM1BA[1:0] | Column Address | |||||||||
0 | 3 | - | Row Address | Column Address | ||||||||||
1 | 3 | - | Row Address | EM1BA[0] | Column Address | |||||||||
2 | 3 | - | Row Address | EM1BA[1:0] | Column Address |