SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The master clock period (Tmst) is a multiple of the period of the I2C Module Clock (Tmod):
where d depends on the divide-down value IPSC, as shown in Table 19-1. IPSC is described in the I2CPSC register.
IPSC | d |
---|---|
0 | 7 |
1 | 6 |
Greater than 1 | 5 |