SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The block diagram in Figure 14-5 shows the critical signals and registers of the time-base submodule. Table 14-2 provides descriptions of the key signals associated with the time-base submodule.
Signal | Description |
---|---|
EPWMxSYNCI | Time-base synchronization input. |
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM module in each synchronization chain, this signal can come from a device pin using INPUT5 or INPUT6 of the Input X-BAR or from a previous ePWM module. For subsequent ePWM modules in each chain, this signal is passed from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral, EPWM3SYNCI is generated by ePWM2 and so forth. For information on the synchronization order of a particular device, see Section 14.4.3.3. | |
EPWMxSYNCO | Time-base synchronization output. |
This output
pulse is used to synchronize the counter of an ePWM module later
in the synchronization chain. The ePWM module generates this
signal from one of three event sources:
|
|
EPWMxSYNCPER | Time-base peripheral synchronization output. |
This output signal is used to synchronize the GPDAC and CMPSS to the EPWM. The output signal can be configured using the HRPCTL register. Note that this signal has no relation with the HRPWM. | |
CTR = PRD | Time-base counter equal to the specified period. |
This signal is generated whenever the counter value is equal to the active period register value. That is when TBCTR = TBPRD. | |
CTR = Zero | Time-base counter equal to zero |
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00. | |
CTR = CMPB | Time-base counter equal to active counter-compare B register (TBCTR = CMPB). |
This event is generated by the counter-compare submodule and used by the synchronization out logic | |
CTR_dir | Time-base counter direction. |
Indicates the current direction of the ePWM's time-base counter. The signal is high when the counter is increasing and the signal is low when the counter is decreasing. | |
CTR_max | Time-base counter equal max value. (TBCTR = 0xFFFF) |
Generated event when the TBCTR value reaches the maximum value. This signal is only used only as a status bit | |
TBCLK | Time-base clock. |
This is a prescaled version of the ePWM clock (EPWMCLK) and is used by all submodules within the ePWM. This clock determines the rate at which time-base counter increments or decrements. |