SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in Table 20-22.
Register | Bit | Name | Function | Type | Reset Value | |
---|---|---|---|---|---|---|
SPCR1 | 12-11 | CLKSTP | Clock stop mode | R/W | 00 | |
CLKSTP = 0Xb | Clock stop mode disabled; normal clocking for non-SPI mode | |||||
CLKSTP = 10b | Clock stop mode enabled, without clock delay | |||||
CLKSTP = 11b | Clock stop mode enabled, with clock delay |
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol, you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on the MCLKR pin.
Table 20-23 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization signal is tied internally to the transmit frame-synchronization signal.
Bit Settings | Clock Scheme |
---|---|
CLKSTP = 00b or 01b | Clock stop mode disabled. Clock enabled for non-SPI mode. |
CLKXP = 0 or 1 | |
CLKRP = 0 or 1 | |
CLKSTP = 10b | Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and receives data on the falling edge of MCLKR. |
CLKXP = 0 | |
CLKRP = 0 | |
CLKSTP = 11b | Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising edge of CLKX and receives data on the rising edge of MCLKR. |
CLKXP = 0 | |
CLKRP = 1 | |
CLKSTP = 10b | High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and receives data on the rising edge of MCLKR. |
CLKXP = 1 | |
CLKRP = 0 | |
CLKSTP = 11b | High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and receives data on the falling edge of MCLKR. |
CLKXP = 1 | |
CLKRP = 1 |