SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held low long enough to reset other system ICs, but some applications can require a longer pulse. In these cases, XRS can be driven low externally to provide the correct reset duration. A POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag register (NMISHDFLG), the X1 clock counter register (X1CNT), and the hibernate configuration registers (HIBBOOTMODE, IORESTOREADDR, and LPMCR.M0M1MODE).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.