SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
Three clock domains are provided to the CAN module for generating the CAN bit timing: the external clock (X1/X2), the system clock (SYSCLK), and the GPIO_AUXCLKIN.
The System Control and Interrupts chapter and the device data sheet provide more information on how to configure the relevant clock source registers in the system module.