SPRUHX5I August 2014 – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is part of the device's clock enable registers and is described in the System Control and Interrupts section of this manual. When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is: