SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Uses for eCAP include:
The eCAP module includes the following features:
The eCAP module represents one complete capture channel that can be instantiated multiple times depending on the target device. In the context of this guide, one eCAP channel has the following independent key resources:
Multiple identical eCAP modules can be contained in a system as shown in Figure 29-53. For actual number of eCAP modules integrated in the device, refer to the Section 29.1.3. As already described in Section 29.1.3, the letter x within a signal or module name is used to indicate a generic eCAP instance on a device. For example, output interrupt request, ECAP1INT belongs to eCAP1, ECAP2INT belongs to eCAP2, etc.
The eCAP module resources can be used to implement a single-channel PWM generator (with 32 bit capabilities) when it is not being used for input captures. The counter operates in count-up mode, providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The PWMSS_ECAP_CAP1 and PWMSS_ECAP_CAP2 registers become the active period and compare registers, respectively, while PWMSS_ECAP_CAP3 and PWMSS_ECAP_CAP4 registers become the period and capture shadow registers, respectively. Figure 29-54 is a high-level view of both the capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 29-55 shows the various components that implement the capture function.
An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the prescaler. This is useful when very high frequency signals are used as inputs. Figure 29-56 shows a functional diagram and Figure 29-57 shows the operation of the prescale function.
The continuous/one-shot block (Figure 29-58) controls the start/stop and reset (zero) functions of the Mod4 counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both the Mod4 counter and contents of PWMSS_ECAP_CAP1-4 registers (time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the Mod4 counter and permits loading of PWMSS_ECAP_CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored, and capture values continue to be written to PWMSS_ECAP_CAP1-4 in a circular buffer sequence.
This counter (Figure 29-59) provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4 signals.
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a time-stamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
PWMSS_ECAP_CAP1 and PWMSS_ECAP_CAP2 registers become the active period and compare registers, respectively, in APWM mode.
PWMSS_ECAP_CAP3 and PWMSS_ECAP_CAP4 registers become the respective shadow registers (APRD and ACMP) for PWMSS_ECAP_CAP1 and PWMSS_ECAP_CAP2 during APWM operation.
An Interrupt can be generated on capture events (CEVT1-CEVT4, CNTOVF) or APWM events (TSCNT = PRD, TSCNT = CMP). See Figure 29-60.
A counter overflow event (FFFF FFFFh->0000 0000h) is also provided as an interrupt source (CNTOVF).
The capture events are edge and sequencer qualified (that is, ordered in time) by the polarity select and Mod4 gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPn module) going to the interrupt controller.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, TSCNT = PRD, TSCNT = CMP) can be generated. The interrupt enable register (PWMSS_ECAP_ECEINT) is used to enable/disable individual interrupt event sources. The interrupt flag register (PWMSS_ECAP_ECFLG) indicates if any interrupt event has been latched and contains the global interrupt flag bit (INT). An interrupt pulse is generated to the interrupt controller only if any of the interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must clear the global interrupt flag bit and the serviced event via the interrupt clear register (PWMSS_ECAP_ECCLR) before any other interrupt pulses are generated. You can force an interrupt event via the interrupt force register (PWMSS_ECAP_ECFRC). This is useful for test purposes.
In capture mode, this logic inhibits (locks out) any shadow loading of PWMSS_ECAP_CAP1 or PWMSS_ECAP_CAP2 from APRD and ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode (PWMSS_ECAP_ECCTL2[9] CAPAPWM == 0). The TSCNT = PRD, TSCNT = CMP flags are only valid in APWM mode (PWMSS_ECAP_ECCTL2[9] CAPAPWM == 1). CNTOVF flag is valid in both modes.
Main operating highlights of the APWM section:
The behavior of APWM active-high mode (APWMPOL == 0) is:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period
The behavior of APWM active-low mode (APWMPOL == 1) is:
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
CMP > PERIOD+1, output low for complete period
Table 29-111 shows the eCAP module control and status register set. All 32-bit registers are aligned on even address boundaries and are organized in little-endian mode. The 16 least-significant bits of a 32-bit register are located on lowest address (even address).
In APWM mode, writing to PWMSS_ECAP_CAP1/PWMSS_ECAP_CAP2 active registers also writes the same value to the corresponding shadow registers PWMSS_ECAP_CAP3/PWMSS_ECAP_CAP4. This emulates immediate mode. Writing to the shadow registers PWMSS_ECAP_CAP3/PWMSS_ECAP_CAP4 invokes the shadow mode.
Offset | Register Name | Description | Size (×16) |
---|---|---|---|
0h | PWMSS_ECAP_TSCNT | Time-Stamp Counter Register | 2 |
4h | PWMSS_ECAP_CNTPHS | Counter Phase Offset Value Register | 2 |
8h | PWMSS_ECAP_CAP1 | Capture 1 Register | 2 |
Ch | PWMSS_ECAP_CAP2 | Capture 2 Register | 2 |
10h | PWMSS_ECAP_CAP3 | Capture 3 Register | 2 |
14h | PWMSS_ECAP_CAP4 | Capture 4 Register | 2 |
28h | PWMSS_ECAP_ECCTL1 | Capture Control Register 1 | 1 |
2Ah | PWMSS_ECAP_ECCTL2 | Capture Control Register 2 | 1 |
2Ch | PWMSS_ECAP_ECEINT | Capture Interrupt Enable Register | 1 |
2Eh | PWMSS_ECAP_ECFLG | Capture Interrupt Flag Register | 1 |
30h | PWMSS_ECAP_ECCLR | Capture Interrupt Clear Register | 1 |
32h | PWMSS_ECAP_ECFRC | Capture Interrupt Force Register | 1 |
5Ch | PWMSS_ECAP_PID | Revision ID Register | 2 |
This section provides description of the PWMSS eCAP relevant functional registers.
Module Name | Module Base Address L4_PER2 Interconnect | Size (Bytes) |
---|---|---|
PWMSS1_ECAP | 0x4843 E100 | 400 Bytes |
PWMSS2_ECAP | 0x4844 0100 | 400 Bytes |
PWMSS3_ECAP | 0x4844 2100 | 400 Bytes |
Register Name | Type | Register Width (Bits) | Address Offset | PWMSS1_ECAP Physical Address L4_PER2 Interconnect | PWMSS2_ECAP Physical Address L4_PER2 Interconnect | PWMSS3_ECAP Physical Address L4_PER2 Interconnect |
---|---|---|---|---|---|---|
PWMSS_ECAP_TSCNT | RW | 32 | 0x0 | 0x4843 E100 | 0x4844 0100 | 0x4844 2100 |
PWMSS_ECAP_CNTPHS | RW | 32 | 0x4 | 0x4843 E104 | 0x4844 0104 | 0x4844 2104 |
PWMSS_ECAP_CAP1 | RW | 32 | 0x8 | 0x4843 E108 | 0x4844 0108 | 0x4844 2108 |
PWMSS_ECAP_CAP2 | RW | 32 | 0xC | 0x4843 E10C | 0x4844 010C | 0x4844 210C |
PWMSS_ECAP_CAP3 | RW | 32 | 0x10 | 0x4843 E110 | 0x4844 0110 | 0x4844 2110 |
PWMSS_ECAP_CAP4 | RW | 32 | 0x14 | 0x4843 E114 | 0x4844 0114 | 0x4844 2114 |
PWMSS_ECAP_ECCTL1 | RW | 16 | 0x28 | 0x4843 E128 | 0x4844 0128 | 0x4844 2128 |
PWMSS_ECAP_ECCTL2 | RW | 16 | 0x2A | 0x4843 E12A | 0x4844 012A | 0x4844 212A |
PWMSS_ECAP_ECEINT | RW | 16 | 0x2C | 0x4843 E12C | 0x4844 012C | 0x4844 212C |
PWMSS_ECAP_ECFLG | R | 16 | 0x2E | 0x4843 E12E | 0x4844 012E | 0x4844 212E |
PWMSS_ECAP_ECCLR | RW | 16 | 0x30 | 0x4843 E130 | 0x4844 0130 | 0x4844 2130 |
PWMSS_ECAP_ECFRC | RW | 16 | 0x32 | 0x4843 E132 | 0x4844 0132 | 0x4844 2132 |
PWMSS_ECAP_PID | R | 32 | 0x5C | 0x4843 E15C | 0x4844 015C | 0x4844 215C |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4843 E100 0x4844 0100 0x4844 2100 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Time Stamp Counter Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSCNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TSCNT | Active 32 bit-counter register that is used as the capture time-base | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4843 E104 0x4844 0104 0x4844 2104 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Counter Phase Control Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNTPHS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CNTPHS | Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded into PWMSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases. | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4843 E108 0x4844 0108 0x4844 2108 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Capture-1 Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CAP1 | This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode. | RW | 0x0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4843 E10C 0x4844 010C 0x4844 210C | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Capture-2 Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CAP2 | This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode. | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4843 E110 0x4844 0110 0x4844 2110 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Capture-3 Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CAP3 | In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User SW updates the PWM period value through this register. In this mode, CAP3 shadows CAP1. | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4843 E114 0x4844 0114 0x4844 2114 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | Capture-4 Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CAP4 | In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User SW updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2. | RW | 0x0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4843 E128 0x4844 0128 0x4844 2128 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Control Register1 | ||
Type | RW |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREE_SOFT | EVTFLTPS | CAPLDEN | CTRRST4 | CAP4POL | CTRRST3 | CAP3POL | CTRRST2 | CAP2POL | CTRRST1 | CAP1POL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:14 | FREE_SOFT | Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free). | RW | 0x0 |
13:9 | EVTFLTPS | Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 ... 0x1E = Divide by 60 0x1F = Divide by 62 | RW | 0x0 |
8 | CAPLDEN | Enable Loading of PWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time. | RW | 0x0 |
7 | CTRRST4 | Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation) | RW | 0x0 |
6 | CAP4POL | Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE) | RW | 0x0 |
5 | CTRRST3 | Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation) | RW | 0x0 |
4 | CAP3POL | Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE) | RW | 0x0 |
3 | CTRRST2 | Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation) | RW | 0x0 |
2 | CAP2POL | Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE) | RW | 0x0 |
1 | CTRRST1 | Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation) | RW | 0x0 |
0 | CAP1POL | Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE) | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 002A | ||
Physical Address | 0x4843 E12A 0x4844 012A 0x4844 212A | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Control Register 2 | ||
Type | RW |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | APWMPOL | CAPAPWM | SWSYNC | SYNCO_SEL | SYNCI_EN | TSCNTSTP | REARMRESET | STOPVALUE | CONTONESHT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:11 | RESERVED | R | 0x0 | |
10 | APWMPOL | APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time) | RW | 0x0 |
9 | CAPAPWM | CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration. | RW | 0x0 |
8 | SWSYNC | Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the TSCNT = PRD event. Note: Selection TSCNT = PRD is meaningful only in APWM mode. However, you can choose it in CAP mode if you find doing so useful. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0b00. After writing a 1, this bit returns to a zero. | RW | 0x0 |
7:6 | SYNCO_SEL | Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select TSCNT = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal | RW | 0x0 |
5 | SYNCI_EN | Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from PWMSS_ECAP_CNTPHS register upon either a SYNCI signal or a S/W force event. | RW | 0x0 |
4 | TSCNTSTP | Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running | RW | 0x0 |
3 | REARMRESET | One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads. | RW | 0x0 |
2:1 | STOPVALUE | Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode. | RW | 0x3 |
0 | CONTONESHT | Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4843 E12C 0x4844 012C 0x4844 212C | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Interrupt Enable Register | ||
Type | RW |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:8 | RESERVED | R | 0x0 | |
7 | CMPEQ | Counter Equal Compare Interrupt Enable. 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source. | RW | 0x0 |
6 | PRDEQ | Counter Equal Period Interrupt Enable. 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source. | RW | 0x0 |
5 | CNTOVF | Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source. | RW | 0x0 |
4 | CEVT4 | Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source. | RW | 0x0 |
3 | CEVT3 | Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source. | RW | 0x0 |
2 | CEVT2 | Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source. | RW | 0x0 |
1 | CEVT1 | Capture Event 1 Interrupt Enable . 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source. | RW | 0x0 |
0 | RESERVED | R | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 002E | ||
Physical Address | 0x4843 E12E 0x4844 012E 0x4844 212E | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Interrupt Flag Register | ||
Type | R |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | INT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:8 | RESERVED | R | 0x0 | |
7 | CMPEQ | Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP) | R | 0x0 |
6 | PRDEQ | Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset. | R | 0x0 |
5 | CNTOVF | Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000 | R | 0x0 |
4 | CEVT4 | Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin | R | 0x0 |
3 | CEVT3 | Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin. | R | 0x0 |
2 | CEVT2 | Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin. | R | 0x0 |
1 | CEVT1 | Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin. | R | 0x0 |
0 | INT | Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated. | R | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4843 E130 0x4844 0130 0x4844 2130 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Interrupt Clear Register | ||
Type | RW |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | INT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:8 | RESERVED | R | 0x0 | |
7 | CMPEQ | Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=CMP flag condition | RW | 0x0 |
6 | PRDEQ | Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=PRD flag condition | RW | 0x0 |
5 | CNTOVF | Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition | RW | 0x0 |
4 | CEVT4 | Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition. | RW | 0x0 |
3 | CEVT3 | Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition. | RW | 0x0 |
2 | CEVT2 | Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition. | RW | 0x0 |
1 | CEVT1 | Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition. | RW | 0x0 |
0 | INT | Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. | RW | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4843 E132 0x4844 0132 0x4844 2132 | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Interrupt Forcing Register | ||
Type | RW |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
15:8 | RESERVED | R | 0x0 | |
7 | CMPEQ | Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=CMP flag bit. | RW | 0x0 |
6 | PRDEQ | Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=PRD flag bit. | RW | 0x0 |
5 | CNTOVF | Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit. | RW | 0x0 |
4 | CEVT4 | Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit | RW | 0x0 |
3 | CEVT3 | Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit | RW | 0x0 |
2 | CEVT2 | Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit. | RW | 0x0 |
1 | CEVT1 | Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit. | RW | 0x0 |
0 | RESERVED | R | 0x0 |
Enhanced Capture (eCAP) Module |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4843 E15C 0x4844 015C 0x4844 215C | Instance | PWMSS1_ECAP PWMSS2_ECAP PWMSS3_ECAP |
Description | ECAP Revision ID | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | IP Revision | R | 0x-(1) |
Enhanced Capture (eCAP) Module |