SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Register Name | Type | Register Width (Bits) | Address Offset | CAL L4_PER2 Physical Address |
---|---|---|---|---|
CAL_HL_REVISION | R | 32 | 0x0000 0000 | 0x4845 B000 |
CAL_HL_HWINFO | R | 32 | 0x0000 0004 | 0x4845 B004 |
CAL_HL_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4845 B010 |
CAL_HL_IRQ_EOI | RW | 32 | 0x0000 001C | 0x4845 B01C |
CAL_HL_IRQSTATUS_RAW_j | RW | 32 | 0x0000 0020 + (0x10 * j) | 0x4845 B020 + (0x10 * j) |
CAL_HL_IRQSTATUS_j | RW | 32 | 0x0000 0024 + (0x10 * j) | 0x4845 B024 + (0x10 * j) |
CAL_HL_IRQENABLE_SET_j | RW | 32 | 0x0000 0028 + (0x10 * j) | 0x4845 B028 + (0x10 * j) |
CAL_HL_IRQENABLE_CLR_j | RW | 32 | 0x0000 002C + (0x10 * j) | 0x4845 B02C + (0x10 * j) |
CAL_PIX_PROC_i | RW | 32 | 0x0000 00C0 + (0x4 * i) | 0x4845 B0C0 + (0x4 * i) |
CAL_CTRL | RW | 32 | 0x0000 0100 | 0x4845 B100 |
CAL_CTRL1 | RW | 32 | 0x0000 0104 | 0x4845 B104 |
CAL_LINE_NUMBER_EVT | RW | 32 | 0x0000 0108 | 0x4845 B108 |
CAL_VPORT_CTRL1 | RW | 32 | 0x0000 0120 | 0x4845 B120 |
CAL_VPORT_CTRL2 | RW | 32 | 0x0000 0124 | 0x4845 B124 |
CAL_BYS_CTRL1 | RW | 32 | 0x0000 0130 | 0x4845 B130 |
CAL_BYS_CTRL2 | RW | 32 | 0x0000 0134 | 0x4845 B134 |
CAL_RD_DMA_CTRL | RW | 32 | 0x0000 0140 | 0x4845 B140 |
CAL_RD_DMA_PIX_ADDR | RW | 32 | 0x0000 0144 | 0x4845 B144 |
CAL_RD_DMA_PIX_OFST | RW | 32 | 0x0000 0148 | 0x4845 B148 |
CAL_RD_DMA_XSIZE | RW | 32 | 0x0000 014C | 0x4845 B14C |
CAL_RD_DMA_YSIZE | RW | 32 | 0x0000 0150 | 0x4845 B150 |
CAL_RD_DMA_INIT_ADDR | RW | 32 | 0x0000 0154 | 0x4845 B154 |
CAL_RD_DMA_INIT_OFST | RW | 32 | 0x0000 0168 | 0x4845 B168 |
CAL_RD_DMA_CTRL2 | RW | 32 | 0x0000 016C | 0x4845 B16C |
CAL_WR_DMA_CTRL_k | RW | 32 | 0x0000 0200 + (0x10 * k) | 0x4845 B200 + (0x10 * k) |
CAL_WR_DMA_ADDR_k | RW | 32 | 0x0000 0204 + (0x10 * k) | 0x4845 B204 + (0x10 * k) |
CAL_WR_DMA_OFST_k | RW | 32 | 0x0000 0208 + (0x10 * k) | 0x4845 B208 + (0x10 * k) |
CAL_WR_DMA_XSIZE_k | RW | 32 | 0x0000 020C + (0x10 * k) | 0x4845 B20C + (0x10 * k) |
CAL_CSI2_PPI_CTRL_l | RW | 32 | 0x0000 0300 + (0x80 * l) | 0x4845 B300 + (0x80 * l) |
CAL_CSI2_COMPLEXIO_CFG_l | RW | 32 | 0x0000 0304 + (0x80 * l) | 0x4845 B304 + (0x80 * l) |
CAL_CSI2_COMPLEXIO_IRQSTATUS_l | RW | 32 | 0x0000 0308 + (0x80 * l) | 0x4845 B308 + (0x80 * l) |
CAL_CSI2_SHORT_PACKET_l | R | 32 | 0x0000 030C + (0x80 * l) | 0x4845 B30C + (0x80 * l) |
CAL_CSI2_COMPLEXIO_IRQENABLE_l | RW | 32 | 0x0000 0310 + (0x80 * l) | 0x4845 B310 + (0x80 * l) |
CAL_CSI2_TIMING_l | RW | 32 | 0x0000 0314 + (0x80 * l) | 0x4845 B314 + (0x80 * l) |
CAL_CSI2_VC_IRQENABLE_l | RW | 32 | 0x0000 0318 + (0x80 * l) | 0x4845 B318 + (0x80 * l) |
CAL_CSI2_VC_IRQSTATUS_l | RW | 32 | 0x0000 0328 + (0x80 * l) | 0x4845 B328 + (0x80 * l) |
CAL_CSI2_CTX0_l | RW | 32 | 0x0000 0330 + (0x80 * l) | 0x4845 B330 + (0x80 * l) |
CAL_CSI2_CTX1_l | RW | 32 | 0x0000 0334 + (0x80 * l) | 0x4845 B334 + (0x80 * l) |
CAL_CSI2_CTX2_l | RW | 32 | 0x0000 0338 + (0x80 * l) | 0x4845 B338 + (0x80 * l) |
CAL_CSI2_CTX3_l | RW | 32 | 0x0000 033C + (0x80 * l) | 0x4845 B33C + (0x80 * l) |
CAL_CSI2_CTX4_l | RW | 32 | 0x0000 0340 + (0x80 * l) | 0x4845 B340 + (0x80 * l) |
CAL_CSI2_CTX5_l | RW | 32 | 0x0000 0344 + (0x80 * l) | 0x4845 B344 + (0x80 * l) |
CAL_CSI2_CTX6_l | RW | 32 | 0x0000 0348 + (0x80 * l) | 0x4845 B348 + (0x80 * l) |
CAL_CSI2_CTX7_l | RW | 32 | 0x0000 034C + (0x80 * l) | 0x4845 B34C + (0x80 * l) |
CAL_CSI2_STATUS0_l | R | 32 | 0x0000 0350 + (0x80 * l) | 0x4845 B350 + (0x80 * l) |
CAL_CSI2_STATUS1_l | R | 32 | 0x0000 0354 + (0x80 * l) | 0x4845 B354 + (0x80 * l) |
CAL_CSI2_STATUS2_l | R | 32 | 0x0000 0358 + (0x80 * l) | 0x4845 B358 + (0x80 * l) |
CAL_CSI2_STATUS3_l | R | 32 | 0x0000 035C + (0x80 * l) | 0x4845 B35C + (0x80 * l) |
CAL_CSI2_STATUS4_l | R | 32 | 0x0000 0360 + (0x80 * l) | 0x4845 B360 + (0x80 * l) |
CAL_CSI2_STATUS5_l | R | 32 | 0x0000 0364 + (0x80 * l) | 0x4845 B364 + (0x80 * l) |
CAL_CSI2_STATUS6_l | R | 32 | 0x0000 0368 + (0x80 * l) | 0x4845 B368 + (0x80 * l) |
CAL_CSI2_STATUS7_l | R | 32 | 0x0000 036C + (0x80 * l) | 0x4845 B36C + (0x80 * l) |