SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The below Table 30-326 shows the read and write format of the 32-bit MII Management interface frames, respectively.
Pre-amble | Start Delimiter | Operation Code | PHY Address | Register Address | Turnaround | Data |
---|---|---|---|---|---|---|
MDIO Read Frame Format | ||||||
0xFFFFFFFF | 01 | 10 | AAAAA | RRRRR | Z0 | DDDD.DDDD.DDDD.DDDD |
MDIO Write Frame Format | ||||||
0xFFFFFFFF | 01 | 00 | AAAAA | RRRRR | 10 | DDDD.DDDD.DDDD.DDDD |
The default or idle state of the two wire serial interface is a logic one. All tri-state drivers should be disabled and the PHY’s pull-up resistor will pull the MDIO line to a logic one. Prior to initiating any other transaction, the station management entity shall send a preamble sequence of 32 contiguous logic one bits on the MDIO line with 32 corresponding cycles on MDCLK to provide the PHY with a pattern that it can use to establish synchronization. A PHY shall observe a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding MDCLK cycles before it responds to any other transaction.
Preamble
The start of a frame is indicated by a preamble, which consists of a sequence of 32 contiguous bits all of which are a “1”. This sequence provides the Ethernet PHY a pattern to use to establish synchronization.
Start Delimiter
The preamble is followed by the start delimiter which is indicated by a “01” pattern. The pattern assures transitions from the default logic one state to zero and back to one.
Operation Code
The operation code for a read is “10”, while the operation code for a write is a “00”.
Ethernet PHY Address
The PHY address is 5 bits allowing 32 unique values. The first bit transmitted is the MSB of the PHY address.
Register Address
The Register address is 5 bits allowing 32 registers to be addressed within each PHY. Refer to the 10/100 PHY address map for addresses of individual registers.
Turnaround
An idle bit time during which no device actively drives the MDIO signal shall be inserted between the register address field and the data field of a read frame in order to avoid contention. During a read frame, the PHY shall drive a zero bit onto MDIO for the first bit time following the idle bit and preceding the Data field. During a write frame, this field shall consist of a one bit followed by a zero bit.
Data
The Data field is 16 bits. The first bit transmitted and received is the MSB of the data word.
The Table 30-327 shows the PRU-ICSS1 / PRU-ICSS2 MII MDIO signals and their availability at the device boundary.
MDIO Control Signals | |||
---|---|---|---|
Pin Name | Type | Available as device I/O | Function |
MDIO_LINKINT[1:0] | O | N.A. | Serial interface link change interrupt. Indicates a change in the state of the PHY link. |
MDIO_USERINT[1:0] | O | N.A. | Serial interface user command event complete interrupt. |
MDIO Interface Signals | |||
Pin Name | Type | Available as device I/O | Function |
MDIO_I | I | device bidi pr1_mdio_data and pr2_mdio_mdclk pin in input mode | Serial data input |
MDIO_O | O | device bidi pr1_mdio_data pr2_mdio_mdclk pin in output mode | Serial data output |
MDIO_OE_N | O | N.A. | Serial data output enable. Asserted "0" when data output is valid |
MDCLK_O | O | device output - pr1_mdio_mdclk pr2_mdio_mdclk | Serial clock output |
MLINK_I[1:0] | I | N.A. | Optional link status inputs from PHY. Each input is connected to a single PHY. Unused inputs are tied ‘0’. |