SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The layer consists of lane merger logic in order to merge the incoming serial stream into a byte stream. The bits are send with LSB first. The number of active lanes is configurable through register. The order of the lanes at the CSI-2 receiver core is also configurable. The number of lanes can be changed only in ULPM or when all data lanes are in "stop state" (OFF mode).
The lane merger can merge up to four lanes into a single byte stream, and is not used for a single lane.
Figure 8-11 to Figure 8-14 show the byte position into each serial link for one to four data lane configurations. The byte stream always starts from lane 1. It finishes on one of the lanes, depending on the number of bytes to receive and the number of lanes.
The following configuration is supported on the AM571x family of devices:
The following configuration is supported on the AM570x family of devices:
See Table 8-1, CAMSS I/O Description, and a device-specific Data Manual, for more details.