SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4AE0 7D00 | Instance | DEVICE_PRM |
Description | Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read returns 0 only. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RST_GLOBAL_COLD_SW | RST_GLOBAL_WARM_SW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1 | RST_GLOBAL_COLD_SW | Global COLD software reset control. This bit is reset only upon a global cold source of reset. | RW | 0x0 |
0x0: Global COLD software reset is cleared. | ||||
0x1: Triggers a global COLD software reset. The software must ensure the SDRAM is properly put in sef-refresh mode before applying this reset. | ||||
0 | RST_GLOBAL_WARM_SW | Global WARM software reset control. This bit is reset upon any global source of reset (warm and cold). | RW | 0x0 |
0x0: Global warm software reset is cleared. | ||||
0x1: Triggers a global warm software reset. |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4AE0 7D04 | Instance | DEVICE_PRM |
Description | This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TSHUT_IVA_RST | TSHUT_DSPEVE_RST | LLI_RST | TSHUT_CORE_RST | TSHUT_MM_RST | TSHUT_MPU_RST | C2C_RST | ICEPICK_RST | VDD_CORE_VOLT_MGR_RST | VDD_MM_VOLT_MGR_RST | VDD_MPU_VOLT_MGR_RST | EXTERNAL_WARM_RST | SECURE_WDT_RST | MPU_WDT_RST | MPU_SECURITY_VIOL_RST | GLOBAL_WARM_SW_RST | GLOBAL_COLD_RST |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:17 | RESERVED | R | 0x0 | |
16 | TSHUT_IVA_RST | TSHUT_IVA warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No TSHUT_MM reset. | ||||
0x1: TSHUT_MM reset has occurred. | ||||
15 | TSHUT_DSPEVE_RST | TSHUT_DSPEVE warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No TSHUT_MM reset. | ||||
0x1: TSHUT_MM reset has occurred. | ||||
14 | LLI_RST | LLI warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No LLI warm reset. | ||||
0x1: LLI warm reset has occurred. | ||||
13 | TSHUT_CORE_RST | TSHUT_CORE warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No TSHUT_CORE reset. | ||||
0x1: TSHUT_CORE reset has occurred. | ||||
12 | TSHUT_MM_RST | TSHUT_GPU warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No TSHUT_MM reset. | ||||
0x1: TSHUT_MM reset has occurred. | ||||
11 | TSHUT_MPU_RST | TSHUT_MPU warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No TSHUT_MPU reset. | ||||
0x1: TSHUT_MPU reset has occurred. | ||||
10 | C2C_RST | C2C warm reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No C2C warm reset. | ||||
0x1: C2C warm reset has occurred. | ||||
9 | ICEPICK_RST | IcePick reset event. This is a source of global warm reset initiated by the emulation. | RW | 0x0 |
0x0: No ICEPICK reset. | ||||
0x1: IcePick reset has occurred. | ||||
8 | VDD_CORE_VOLT_MGR_RST | VDD_CORE voltage manager reset event This is a source of global WARM reset. | RW | 0x0 |
0x0: No VDD_CORE voltage manager reset. | ||||
0x1: VDD_CORE voltage manager reset has occurred. | ||||
7 | VDD_MM_VOLT_MGR_RST | VDD_MM voltage manager reset event This is a source of global WARM reset. | RW | 0x0 |
0x0: No VDD_MM voltage manager reset. | ||||
0x1: VDD_MM voltage manager reset has occurred. | ||||
6 | VDD_MPU_VOLT_MGR_RST | VDD_MPU voltage manager reset event This is a source of global WARM reset. | RW | 0x0 |
0x0: No VDD_MPU voltage manager reset. | ||||
0x1: VDD_MPU voltage manager reset has occurred. | ||||
5 | EXTERNAL_WARM_RST | External warm reset event | RW | 0x0 |
0x0: No global warm reset. | ||||
0x1: Global external warm reset has occurred. | ||||
4 | SECURE_WDT_RST | Secure Watchdog timer or HDCP reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No Secure watchdog / HDCP reset. | ||||
0x1: Secure wachtdog or HDCP reset has occurred. | ||||
3 | MPU_WDT_RST | WD_TIMER2 and MPU subsystem watchdog reset event. This is a source of global WARM reset. | RW | 0x0 |
0x0: No reset. | ||||
0x1: Reset has occurred. | ||||
2 | MPU_SECURITY_VIOL_RST | Security violation reset event triggered by Security State Machine inside MPUSS. This is a source of global WARM reset. | RW | 0x0 |
0x0: No security violation reset. | ||||
0x1: Security violation reset has occurred. | ||||
1 | GLOBAL_WARM_SW_RST | Global warm software reset event | RW | 0x0 |
0x0: No global warm SW reset | ||||
0x1: Global warm SW reset has occurred. | ||||
0 | GLOBAL_COLD_RST | Power-on (cold) reset event | RW | 0x1 |
0x0: No power-on reset. | ||||
0x1: Power-on reset has occurred. |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4AE0 7D08 | Instance | DEVICE_PRM |
Description | Reset duration control. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RSTTIME2 | RSTTIME1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:10 | RSTTIME2 | Power domain reset duration 2 in number of RM.SYSCLK clock cycles. | RW | 0x10 |
0x0: Reserved | ||||
9:0 | RSTTIME1 | Global reset duration 1 in number of FUNC_32K_CLK clock cycles. This bit-field is only sensitive to the external power-on reset (WKUPAON_SYS_PWRON_RST reset line) | RW | 0x6 |
0x0: Reserved |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4AE0 7D10 | Instance | DEVICE_PRM |
Description | This register provides voltage domain management controls. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VDD_MM_I2C_DISABLE | VDD_MPU_I2C_DISABLE | VDD_CORE_I2C_DISABLE | RESERVED | VDD_MM_PRESENCE | VDD_MPU_PRESENCE | RESERVED | AUTO_CTRL_VDD_MM_L | AUTO_CTRL_VDD_MPU_L | AUTO_CTRL_VDD_CORE_L |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | VDD_MM_I2C_DISABLE | This bit allows disabling I2C interface with powerIC for MM voltage (for debug purpose only). [warm reset insensitive] | RW | 0x0 |
0x0: Normal mode: I2C is enabled. | ||||
0x1: Debug mode: I2C is disabled. | ||||
13 | VDD_MPU_I2C_DISABLE | This bit allows disabling I2C interface with powerIC for MPU voltage (for debug purpose only). [warm reset insensitive] | RW | 0x0 |
0x0: Normal mode: I2C is enabled. | ||||
0x1: Debug mode: I2C is disabled. | ||||
12 | VDD_CORE_I2C_DISABLE | This bit allows disabling I2C interface with powerIC for CORE voltage (for debug purpose only). [warm reset insensitive] | RW | 0x0 |
0x0: Normal mode: I2C is enabled. | ||||
0x1: Debug mode: I2C is disabled. | ||||
11:10 | RESERVED | R | 0x0 | |
9 | VDD_MM_PRESENCE | This bit control the presence of MM voltage in device. [warm reset insensitive] | RW | 0x1 |
0x0: MM voltage is not present as an individual voltage: MM voltage is merged with MPU voltage if VDD_MPU_presence=1. MM voltage is merged with CORE voltage if VDD_MPU_presence=0. | ||||
0x1: MM voltage is present on the device. | ||||
8 | VDD_MPU_PRESENCE | This bit control the presence of MPU voltage in device. [warm reset insensitive] | RW | 0x1 |
0x0: MPU voltage is not present as an individual voltage: MPU voltage is merged with MM voltage if VDD_MM_presence=1. MPU voltage is merged with CORE voltage if VDD_MM_presence=0. | ||||
0x1: MPU voltage is present on the device. | ||||
7:6 | RESERVED | R | 0x0 | |
5:4 | AUTO_CTRL_VDD_MM_L | This bit field specifies the state to which the hardware can automatically transition the VDD_MM_L voltage domain. | RW | 0x0 |
0x0: Voltage domain transitions are disabled. | ||||
0x1: Voltage domain transitions to SLEEP are enabled. | ||||
0x2: Voltage domain transitions to RET are enabled. | ||||
0x3: reserved | ||||
3:2 | AUTO_CTRL_VDD_MPU_L | This bit field specifies the state to which the hardware can automatically transition the VDD_MPU_L voltage domain. | RW | 0x0 |
0x0: Voltage domain transitions are disabled. | ||||
0x1: Voltage domain transitions to SLEEP are enabled. | ||||
0x2: Voltage domain transitions to RET are enabled. | ||||
0x3: reserved | ||||
1:0 | AUTO_CTRL_VDD_CORE_L | This bit field specifies the state to which the hardware can automatically transition the VDD_CORE_L voltage domain. | RW | 0x0 |
0x0: Voltage domain transitions are disabled. | ||||
0x1: Voltage domain transitions to SLEEP are enabled. | ||||
0x2: Voltage domain transitions to RET are enabled. | ||||
0x3: reserved |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4AE0 7D14 | Instance | DEVICE_PRM |
Description | This register allows controlling the PWRREQ signal towards power IC. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRREQ_COND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1:0 | PWRREQ_COND | Control upon which condition from MPU, MM and CORE voltage domains PWRREQ is de-asserted. | RW | 0x0 |
0x0: PWRREQ is never de-asserted | ||||
0x1: PWRREQ is de-asserted if all voltage domain are in SLEEP, RET or OFF state. Conversely, PWRREQ is asserted upon any voltage domain entering or staying in ON state. | ||||
0x2: PWRREQ is de-asserted if all voltage domain are in RET or OFF state. Conversely, PWRREQ is asserted upon any voltage domain entering or staying in ON or SLEEP state. | ||||
0x3: PWRREQ is de-asserted if all voltage domain are in OFF state. Conversely, PWRREQ is asserted upon any voltage domain entering or staying in ON or SLEEP or RET state. |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4AE0 7D18 | Instance | DEVICE_PRM |
Description | This register allows controlling 2 parameters for power state controller. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HG_PONOUT_2_PGOODIN_TIME | PONOUT_2_PGOODIN_TIME | PCHARGE_TIME |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23:16 | HG_PONOUT_2_PGOODIN_TIME | The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles. Target is 10us. | RW | 0x30 |
15:8 | PONOUT_2_PGOODIN_TIME | The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles. Target is 10us. | RW | 0x30 |
7:0 | PCHARGE_TIME | Number of system clock cycles for the SRAM pre-charge duration. Target is 600ns. | RW | 0x17 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4AE0 7D1C | Instance | DEVICE_PRM |
Description | This register allows controlling DDR IO isolation removal setup. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ISO_2_ON_TIME |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x0 | |
7:0 | ISO_2_ON_TIME | Determines the setup time of the DDR IOs going out of isolation. Counting on the system clock. Target is 1.5us. | RW | 0x3a |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4AE0 7D20 | Instance | DEVICE_PRM |
Description | This register allows controlling power management features of the IOs. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GLOBAL_WUEN | RESERVED | WUCLK_STATUS | WUCLK_CTRL | RESERVED | IO_ON_STATUS | ISOOVR_EXTEND | RESERVED | ISOCLK_STATUS | ISOCLK_OVERRIDE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:17 | RESERVED | R | 0x0 | |
16 | GLOBAL_WUEN | Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic. | RW | 0x0 |
0x0: All individual IO WUEN are gated in the Spinner logic (overriden to 0). | ||||
0x1: All individual IO WUEN from control module are going to IOs. | ||||
15:10 | RESERVED | R | 0x0 | |
9 | WUCLK_STATUS | Gives value of WUCLKOUT signal coming back from IO pad ring. | R | 0x0 |
8 | WUCLK_CTRL | Direct control on WUCLKIN signal to IO pad ring. | RW | 0x0 |
0x0: WUCLKIN signal is driven to 0. IO wakeup daisy chain is functional as well as IO whose wakeup feature is enabled. | ||||
0x1: WUCLKIN signal is driven to 1. IO wakeup daisy chain is reset and is latching current pad states and WUEN inputs. | ||||
7:6 | RESERVED | R | 0x0 | |
5 | IO_ON_STATUS | Gives the functional status of the IO ring. | R | 0x1 |
0x0: Part or all of the IOs are not in the ON state, that is are in isolation state. | ||||
0x1: All IOs are in the ON state. | ||||
4 | ISOOVR_EXTEND | Control non-EMIF IO isolation extension upon a device wakeup from OFF mode. | RW | 0x0 |
0x0: Non-EMIF IO isolation is not extended. 'EMIF_ON' IO transition happens as soon as automatic restore is completed. | ||||
0x1: Non-EMIF IO isolation is extended. 'EMIF_ON' IO transition is stalled. | ||||
3:2 | RESERVED | R | 0x0 | |
1 | ISOCLK_STATUS | Gives value of ISOCLKOUT signal coming back from IO pad ring. | R | 0x0 |
0 | ISOCLK_OVERRIDE | Override control on ISOCLKIN signal to IO pad ring. Used at boot time when it is needed to change the mode of an IO from 1.8V default mode to 1.2V mode. When not overriden, this signal is controlled by hardware only. | RW | 0x0 |
0x0: ISOCLKIN signal is not overriden. | ||||
0x1: ISOCLKIN signal is overriden to active value ('1'). |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4AE0 7D24 | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage stabilization duration upon a global warm reset. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STABLE_PRESCAL | RESERVED | STABLE_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9:8 | STABLE_PRESCAL | Determines prescaler for stabilization duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 32 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 2048 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 16384 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | STABLE_COUNT | Determines the stabilization duration of all VDD_xxx_L regulators upon a global warm reset assertion. The duration is computed according to Stable_Prescal. | RW | 0x0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4AE0 7D28 | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions with OFF state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_CORE_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted. | RW | 0x0 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4AE0 7D2C | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions to or from OFF state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_MPU_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted. | RW | 0x0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4AE0 7D30 | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MM_L domain transitions to or from OFF state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_MM_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_MM_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_MM_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted. | RW | 0x0 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4AE0 7D34 | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. | RW | 0x0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4AE0 7D38 | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 265 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Up_Prescal. | RW | 0x0 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4AE0 7D3C | Instance | DEVICE_PRM |
Description | This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MM_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMP_DOWN_PRESCAL | RESERVED | RAMP_DOWN_COUNT | RESERVED | RAMP_UP_PRESCAL | RESERVED | RAMP_UP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25:24 | RAMP_DOWN_PRESCAL | Determines prescaler for ramp-down duration counting. | RW | 0x0 |
0x0: Ramp-down counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-down counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-down counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-down counter is incremented every 2048 system clock cycles | ||||
23:22 | RESERVED | R | 0x0 | |
21:16 | RAMP_DOWN_COUNT | Determines the ramp-down duration of VDD_MM_L regulators. The duration is computed according to Ramp_Down_Prescal. | RW | 0x0 |
15:10 | RESERVED | R | 0x0 | |
9:8 | RAMP_UP_PRESCAL | Determines prescaler for ramp-up duration counting. | RW | 0x0 |
0x0: Ramp-up counter is incremented every 64 system clock cycles | ||||
0x1: Ramp-up counter is incremented every 256 system clock cycles | ||||
0x2: Ramp-up counter is incremented every 512 system clock cycles | ||||
0x3: Ramp-up counter is incremented every 2048 system clock cycles | ||||
7:6 | RESERVED | R | 0x0 | |
5:0 | RAMP_UP_COUNT | Determines the ramp-up duration of VDD_MM_L regulators. The duration is computed according to Ramp_Up_Prescal. | RW | 0x0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4AE0 7D40 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERROROFFSET | ERRORGAIN | INITVOLTAGE | RESERVED | TIMEOUTEN | INITVDD | FORCEUPDATE | VPENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ERROROFFSET | Offset value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
23:16 | ERRORGAIN | Gain value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
15:8 | INITVOLTAGE | Set the initial voltage level of the SMPS. | RW | 0x0 |
7:4 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
3 | TIMEOUTEN | Enable or disable the timeout capability of the Voltage Controller State Machine. | RW | 0x0 |
0x0: Timeout is disabled. Loop will wait indefinitely. | ||||
0x1: Timeout will occur when TIMEOUT cycles have elapsed. | ||||
2 | INITVDD | Initializes the voltage in the Voltage Processor. | RW | 0x0 |
0x0: Reset the initialization bit. | ||||
0x1: The positive edge of InitVdd triggers a write of the value in the InitVoltage into the Voltage Processor. | ||||
1 | FORCEUPDATE | Forces an update of the SMPS. | RW | 0x0 |
0x0: Reset the force bit. | ||||
0x1: The positive edge of ForceUpdate triggers an update of the voltage to the SMPS. | ||||
0 | VPENABLE | Enables or disables the Voltage Processor updates on SR_SInterruptz. | RW | 0x0 |
0x0: Disables the Voltage Processor. | ||||
0x1: Enables the Voltage Processor. |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4AE0 7D44 | Instance | DEVICE_PRM |
Description | This register reflects the idle state of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L. This register is read only and automatically updated. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VPINIDLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
0 | VPINIDLE | CORE Voltage Processor idle status. | R | 0x1 |
0x0: The Voltage Processor for CORE is processing. Warm reset sensitive | ||||
0x1: The Voltage Processor for CORE is in idle state. |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4AE0 7D48 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDDMAX | VDDMIN | TIMEOUT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | VDDMAX | Defines the maximum voltage supply level. | RW | 0x0 |
23:16 | VDDMIN | Defines the minimum voltage supply level. | RW | 0x0 |
15:0 | TIMEOUT | Defines Voltage Controller maximum wait time for responses. | RW | 0x0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4AE0 7D4C | Instance | DEVICE_PRM |
Description | This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCEUPDATEWAIT | VPVOLTAGE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | FORCEUPDATEWAIT | The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait can only be used during force_update operation. | RW | 0x111 |
7:0 | VPVOLTAGE | Indicates the current SMPS programmed voltage. | R | 0x0 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4AE0 7D50 | Instance | DEVICE_PRM |
Description | This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMAX | VSTEPMAX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMAX | Slew rate for positive voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMAX | Maximum voltage step | RW | 0x0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4AE0 7D54 | Instance | DEVICE_PRM |
Description | This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMIN | VSTEPMIN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMIN | Slew rate for negative voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMIN | Minimum voltage step | RW | 0x0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4AE0 7D58 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERROROFFSET | ERRORGAIN | INITVOLTAGE | RESERVED | TIMEOUTEN | INITVDD | FORCEUPDATE | VPENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ERROROFFSET | Offset value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
23:16 | ERRORGAIN | Gain value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
15:8 | INITVOLTAGE | Set the initial voltage level of the SMPS. | RW | 0x0 |
7:4 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
3 | TIMEOUTEN | Enable or disable the timeout capability of the Voltage Controller State Machine. | RW | 0x0 |
0x0: Timeout is disabled. Loop will wait indefinitely. | ||||
0x1: Timeout will occur when TIMEOUT cycles have elapsed. | ||||
2 | INITVDD | Initializes the voltage in the Voltage Processor. | RW | 0x0 |
0x0: Reset the initialization bit. | ||||
0x1: The positive edge of InitVdd triggers a write of the value in the InitVoltage into the Voltage Processor. | ||||
1 | FORCEUPDATE | Forces an update of the SMPS. | RW | 0x0 |
0x0: Reset the force bit. | ||||
0x1: The positive edge of ForceUpdate triggers an update of the voltage to the SMPS. | ||||
0 | VPENABLE | Enables or disables the Voltage Processor updates on SR_SInterruptz. | RW | 0x0 |
0x0: Disables the Voltage Processor. | ||||
0x1: Enables the Voltage Processor. |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4AE0 7D5C | Instance | DEVICE_PRM |
Description | This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L. This register is read only and automatically updated. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VPINIDLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
0 | VPINIDLE | Voltage Processor 1 idle status. | R | 0x1 |
0x0: The Voltage Processor 1 is processing. | ||||
0x1: The Voltage Processor 1 is in idle state. |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4AE0 7D60 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDDMAX | VDDMIN | TIMEOUT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | VDDMAX | Defines the maximum voltage supply level. | RW | 0x0 |
23:16 | VDDMIN | Defines the minimum voltage supply level. | RW | 0x0 |
15:0 | TIMEOUT | Defines Voltage Controller maximum wait time for responses. | RW | 0x0 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4AE0 7D64 | Instance | DEVICE_PRM |
Description | This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCEUPDATEWAIT | VPVOLTAGE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | FORCEUPDATEWAIT | The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation. | RW | 0x111 |
7:0 | VPVOLTAGE | Indicates the current SMPS programmed voltage. | R | 0x0 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4AE0 7D68 | Instance | DEVICE_PRM |
Description | This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMAX | VSTEPMAX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMAX | Slew rate for positive voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMAX | Maximum voltage step | RW | 0x0 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4AE0 7D6C | Instance | DEVICE_PRM |
Description | This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMIN | VSTEPMIN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMIN | Slew rate for negative voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMIN | Minimum voltage step | RW | 0x0 |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4AE0 7D70 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the Voltage Processor dedicated to MM Voltage Domain (VDD_MM_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERROROFFSET | ERRORGAIN | INITVOLTAGE | RESERVED | TIMEOUTEN | INITVDD | FORCEUPDATE | VPENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ERROROFFSET | Offset value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
23:16 | ERRORGAIN | Gain value in the Error to Voltage converter (two's complement number). | RW | 0x0 |
15:8 | INITVOLTAGE | Set the initial voltage level of the SMPS. | RW | 0x0 |
7:4 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
3 | TIMEOUTEN | Enable or disable the timeout capability of the Voltage Controller State Machine. | RW | 0x0 |
0x0: Timeout is disabled. Loop will wait indefinitely. | ||||
0x1: Timeout will occur when TIMEOUT cycles have elapsed. | ||||
2 | INITVDD | Initializes the voltage in the Voltage Processor. | RW | 0x0 |
0x0: Reset the initialization bit. | ||||
0x1: The positive edge of InitVdd triggers a write of the value in the InitVoltage into the Voltage Processor. | ||||
1 | FORCEUPDATE | Forces an update of the SMPS. | RW | 0x0 |
0x0: Reset the force bit. | ||||
0x1: The positive edge of ForceUpdate triggers an update of the voltage to the SMPS. | ||||
0 | VPENABLE | Enables or disables the Voltage Processor updates on SR_SInterruptz. | RW | 0x0 |
0x0: Disables the Voltage Processor. | ||||
0x1: Enables the Voltage Processor. |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x4AE0 7D74 | Instance | DEVICE_PRM |
Description | This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MM_L. This register is read only and automatically updated. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VPINIDLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
0 | VPINIDLE | Voltage Processor 1 idle status. | R | 0x1 |
0x0: The Voltage Processor 1 is processing. | ||||
0x1: The Voltage Processor 1 is in idle state. |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x4AE0 7D78 | Instance | DEVICE_PRM |
Description | This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDDMAX | VDDMIN | TIMEOUT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | VDDMAX | Defines the maximum voltage supply level. | RW | 0x0 |
23:16 | VDDMIN | Defines the minimum voltage supply level. | RW | 0x0 |
15:0 | TIMEOUT | Defines Voltage Controller maximum wait time for responses. | RW | 0x0 |
Address Offset | 0x0000 007C | ||
Physical Address | 0x4AE0 7D7C | Instance | DEVICE_PRM |
Description | This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCEUPDATEWAIT | VPVOLTAGE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | FORCEUPDATEWAIT | The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation. | RW | 0x111 |
7:0 | VPVOLTAGE | Indicates the current SMPS programmed voltage. | R | 0x0 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4AE0 7D80 | Instance | DEVICE_PRM |
Description | This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MM voltage Domain (VDD_MM_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMAX | VSTEPMAX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMAX | Slew rate for positive voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMAX | Maximum voltage step | RW | 0x0 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4AE0 7D84 | Instance | DEVICE_PRM |
Description | This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SMPSWAITTIMEMIN | VSTEPMIN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
23:8 | SMPSWAITTIMEMIN | Slew rate for negative voltage step (in number of cycles per step). | RW | 0x0 |
7:0 | VSTEPMIN | Minimum voltage step | RW | 0x0 |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4AE0 7D88 | Instance | DEVICE_PRM |
Description | This register allows the setting of the I2C slave address of the Power IC device, the setting of the voltage configuration register address for the CORE VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register address values for CORE VDD (if used SMPS chips have different command configuration register than voltage configuration register). [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMD_VDD_CORE_L | RACEN_VDD_CORE_L | RAC_VDD_CORE_L | RAV_VDD_CORE_L | SEL_SA_VDD_CORE_L | CMDRA_VDD_CORE_L | VOLRA_VDD_CORE_L | RESERVED | SA_VDD_CORE_L |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
28 | CMD_VDD_CORE_L | Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_CORE_L channel | RW | 0x1 |
0x0: VDD_CORE_L channel use VC_VAL_CMD_VDD_MPU_L set for command values | ||||
0x1: VDD_CORE_L channel use VC_VAL_CMD_VDD_CORE_L set for command values | ||||
27 | RACEN_VDD_CORE_L | Enable bit for usage of RAC_VDD_CORE_L | RW | 0x0 |
0x0: VDD_CORE_L channel uses VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register. | ||||
0x1: VDD_CORE_L channel uses CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register. | ||||
26 | RAC_VDD_CORE_L | Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_CORE_L channel | RW | 0x1 |
0x0: Select CMDRA_VDD_MPU_L for VDD_CORE_L channel | ||||
0x1: Select CMDRA_VDD_CORE_L for VDD_CORE_L channel | ||||
25 | RAV_VDD_CORE_L | Voltage configuration register address pointer for VDD_CORE_L channel. | RW | 0x1 |
0x0: Select VOLRA_VDD_MPU_L for VDD_CORE_L channel | ||||
0x1: Select VOLRA_VDD_CORE_L for VDD_CORE_L channel | ||||
24 | SEL_SA_VDD_CORE_L | Slave address pointer for VDD_CORE_L channel. | RW | 0x0 |
0x0: Select SA_VDD_MPU_L for VDD_CORE_L channel | ||||
0x1: Select SA_VDD_CORE_L for VDD_CORE_L channel | ||||
23:16 | CMDRA_VDD_CORE_L | Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_CORE_L channel.(if VDD_CORE_L source has different command configuration register than voltage VDD_MPU_L) | RW | 0x0 |
15:8 | VOLRA_VDD_CORE_L | Set the voltage configuration register address value for the VDD_CORE_L channel (if VDD_CORE_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register) | RW | 0x0 |
7 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
6:0 | SA_VDD_CORE_L | Set the I2C slave address value for the first Power IC device. | RW | 0x0 |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4AE0 7D8C | Instance | DEVICE_PRM |
Description | This register allows the setting of the I2C slave address of the Power IC device, the setting of the voltage configuration register address for the MM VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register address values for MM VDD (if used SMPS chips have different command configuration register than voltage configuration register).. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMD_VDD_MM_L | RACEN_VDD_MM_L | RAC_VDD_MM_L | RAV_VDD_MM_L | SEL_SA_VDD_MM_L | CMDRA_VDD_MM_L | VOLRA_VDD_MM_L | RESERVED | SA_VDD_MM_L |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
28 | CMD_VDD_MM_L | Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MM_L channel | RW | 0x1 |
0x0: VDD_MM_L channel use VC_VAL_CMD_VDD_MPU_L set for command values | ||||
0x1: VDD_MM_L channel use VC_VAL_CMD_VDD_MM_L set for command values | ||||
27 | RACEN_VDD_MM_L | Enable bit for usage of RAC_VDD_MM_L | RW | 0x0 |
0x0: VDD_MM_L channel uses VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register. | ||||
0x1: VDD_MM_L channel uses CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register. | ||||
26 | RAC_VDD_MM_L | Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MM_L channel | RW | 0x1 |
0x0: Select CMDRA_VDD_MPU_L for VDD_MM_L channel | ||||
0x1: Select CMDRA_VDD_MM_L for VDD_MM_L channel | ||||
25 | RAV_VDD_MM_L | Voltage configuration register address pointer for VDD_MM_L channel. | RW | 0x1 |
0x0: Select VOLRA_VDD_MPU_L for VDD_MM_L channel | ||||
0x1: Select VOLRA_VDD_MM_L for VDD_MM_L channel | ||||
24 | SEL_SA_VDD_MM_L | Slave address pointer for VDD_MM_L channel. | RW | 0x0 |
0x0: Select SA_VDD_MPU_L for VDD_MM_L channel | ||||
0x1: Select SA_VDD_MM_L for VDD_MM_L channel | ||||
23:16 | CMDRA_VDD_MM_L | Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MM_L channel (if VDD_MM_L source has different command configuration register than voltage VDD_MPU_L) | RW | 0x0 |
15:8 | VOLRA_VDD_MM_L | Voltage configuration register address value for VDD_MM_L channel (if VDD_MM_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register) | RW | 0x0 |
7 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
6:0 | SA_VDD_MM_L | Set the I2C slave address value for the second (if any) Power IC device. | RW | 0x0 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4AE0 7D90 | Instance | DEVICE_PRM |
Description | This register allows the setting of the I2C slave address of the Power IC device, the setting of the voltage configuration register address for the MPU VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register address values for MPU VDD (if used SMPS chips have different command configuration register than voltage configuration register). [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMD_VDD_MPU_L | RACEN_VDD_MPU_L | RAC_VDD_MPU_L | RAV_VDD_MPU_L | SEL_SA_VDD_MPU_L | CMDRA_VDD_MPU_L | VOLRA_VDD_MPU_L | RESERVED | SA_VDD_MPU_L |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
28 | CMD_VDD_MPU_L | Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MPU_L channel (This bit has no influence on VDD_MPU_L channel) | RW | 0x0 |
27 | RACEN_VDD_MPU_L | Enable bit for usage of RAC_VDD_MPU_L | RW | 0x0 |
0x0: VDD_MPU_L channel uses VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register. | ||||
0x1: VDD_MPU_L channel uses CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register. | ||||
26 | RAC_VDD_MPU_L | Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MPU_L channel. (This bit has no influence on first VDD_MPU_L channel) | RW | 0x0 |
25 | RAV_VDD_MPU_L | Voltage configuration register address pointer for VDD_MPU_L channel. (This bit has no influence on first VDD_MPU_L channel) | RW | 0x0 |
24 | SEL_SA_VDD_MPU_L | Slave address pointer for VDD_MPU_L channel. (This bit has no influence on first VDD_MPU_L channel) | RW | 0x0 |
23:16 | CMDRA_VDD_MPU_L | Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MPU_L channel. | RW | 0x0 |
15:8 | VOLRA_VDD_MPU_L | Voltage configuration register address value for VDD_MPU_L channel. | RW | 0x0 |
7 | RESERVED | Write 0's for future compatibility. Read is undefined. | R | 0x0 |
6:0 | SA_VDD_MPU_L | Set the I2C slave address value for the third (if any) Power IC device. | RW | 0x0 |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4AE0 7D94 | Instance | DEVICE_PRM |
Description | This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_CORE_L channel. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ON | ONLP | RET | OFF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ON | Set the ON command value. | RW | 0x0 |
23:16 | ONLP | Set the ON-Low-Power command value. | RW | 0x0 |
15:8 | RET | Set the RET command value. | RW | 0x0 |
7:0 | OFF | Set the OFF command value. | RW | 0x0 |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4AE0 7D98 | Instance | DEVICE_PRM |
Description | This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MM_L channel. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ON | ONLP | RET | OFF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ON | Set the ON command value. | RW | 0x0 |
23:16 | ONLP | Set the ON-Low-Power command value. | RW | 0x0 |
15:8 | RET | Set the RET command value. | RW | 0x0 |
7:0 | OFF | Set the OFF command value. | RW | 0x0 |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4AE0 7D9C | Instance | DEVICE_PRM |
Description | This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MPU_L channel. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ON | ONLP | RET | OFF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | ON | Set the ON command value. | RW | 0x0 |
23:16 | ONLP | Set the ON-Low-Power command value. | RW | 0x0 |
15:8 | RET | Set the RET command value. | RW | 0x0 |
7:0 | OFF | Set the OFF command value. | RW | 0x0 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4AE0 7DA0 | Instance | DEVICE_PRM |
Description | Bypass data values register used for bypass command channel to send other configuration information (other then voltage configuration parameters) for SMPS chips which have no other configuration interface then this I2C interface and flag to indicate OPP change to EMIF to allow read/write leveling. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OPP_CHANGE_EMIF_LVL | VALID | DATA | REGADDR | RESERVED | SLAVEADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | R | 0x0 | |
25 | OPP_CHANGE_EMIF_LVL | This bit controls read-write leveling of EMIF memories (DDR3). It must be set in case OPP voltage change is done through Voltage Controller whithout passing through Voltage processor. | RW | 0x0 |
0x0: Enable leveling | ||||
0x1: disable leveling | ||||
24 | VALID | This bit validates the bypass command. It is automatically cleared by HW either after getting the acknowledge back from the SMPS or if an error occurred. | RW | 0x0 |
0x0: The last command send has been acknowledged | ||||
0x1: Pending command is being process | ||||
23:16 | DATA | Data to send to the Power IC device. | RW | 0x0 |
15:8 | REGADDR | Set the address of Power IC device register to configure. | RW | 0x0 |
7 | RESERVED | R | 0x0 | |
6:0 | SLAVEADDR | Set the I2C slave address value. | RW | 0x0 |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4AE0 7DA4 | Instance | DEVICE_PRM |
Description | This debug register logs CORE related error status coming from Voltage Controller. Must be cleared by software. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VFSM_TIMEOUT_ERR_CORE | VFSM_RA_ERR_CORE | VFSM_SA_ERR_CORE | SMPS_TIMEOUT_ERR_CORE | SMPS_RA_ERR_CORE | SMPS_SA_ERR_CORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x0 | |
5 | VFSM_TIMEOUT_ERR_CORE | CORE voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
4 | VFSM_RA_ERR_CORE | Wrong register address error for CORE voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
3 | VFSM_SA_ERR_CORE | Wrong slave address error for CORE voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
2 | SMPS_TIMEOUT_ERR_CORE | CORE voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
1 | SMPS_RA_ERR_CORE | Wrong register address error for CORE voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
0 | SMPS_SA_ERR_CORE | Wrong slave address error for CORE voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4AE0 7DA8 | Instance | DEVICE_PRM |
Description | This debug register logs MM related error status coming from Voltage Controller. Must be cleared by software. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VFSM_TIMEOUT_ERR_MM | VFSM_RA_ERR_MM | VFSM_SA_ERR_MM | SMPS_TIMEOUT_ERR_MM | SMPS_RA_ERR_MM | SMPS_SA_ERR_MM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x0 | |
5 | VFSM_TIMEOUT_ERR_MM | MM voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
4 | VFSM_RA_ERR_MM | Wrong register address error for MM voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
3 | VFSM_SA_ERR_MM | Wrong slave address error for MM voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
2 | SMPS_TIMEOUT_ERR_MM | MM voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
1 | SMPS_RA_ERR_MM | Wrong register address error for MM voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
0 | SMPS_SA_ERR_MM | Wrong slave address error for MM voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4AE0 7DAC | Instance | DEVICE_PRM |
Description | This debug register logs MPU related error status coming from Voltage Controller. Must be cleared by software. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VFSM_TIMEOUT_ERR_MPU | VFSM_RA_ERR_MPU | VFSM_SA_ERR_MPU | SMPS_TIMEOUT_ERR_MPU | SMPS_RA_ERR_MPU | SMPS_SA_ERR_MPU |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x0 | |
5 | VFSM_TIMEOUT_ERR_MPU | MPU voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
4 | VFSM_RA_ERR_MPU | Wrong register address error for MPU voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
3 | VFSM_SA_ERR_MPU | Wrong slave address error for MPU voltage FSM | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
2 | SMPS_TIMEOUT_ERR_MPU | MPU voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
1 | SMPS_RA_ERR_MPU | Wrong register address error for MPU voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
0 | SMPS_SA_ERR_MPU | Wrong slave address error for MPU voltage processor | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4AE0 7DB0 | Instance | DEVICE_PRM |
Description | This debug register logs BYPASS related error status coming from Voltage Controller. Must be cleared by software. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BYPS_TIMEOUT_ERR | BYPS_RA_ERR | BYPS_SA_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:3 | RESERVED | R | 0x0 | |
2 | BYPS_TIMEOUT_ERR | BYPASS command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
1 | BYPS_RA_ERR | Wrong register address error for BYPASS command | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged | ||||
0 | BYPS_SA_ERR | Wrong slave address error for BYPASS command | RW | 0x0 |
0x0: No error | ||||
0x1: An error has been logged |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x4AE0 7DB4 | Instance | DEVICE_PRM |
Description | I2C configuration register. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DFILTEREN | RESERVED | SRMODEEN | HSMODEEN | HSMCODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6 | DFILTEREN | This field enables double filter procedure for I2C input lines | RW | 0x0 |
0x0: I2C bus digital filter rejects all glitches smaller than 1 sytem clock cycle | ||||
0x1: I2C bus digital filter rejects all glitches smaller than 2 sytem clock cycle | ||||
5 | RESERVED | R | 0x0 | |
4 | SRMODEEN | Enables the I2C repeated start operation mode (effect of holding the SCL and SDA lines low, in effect blocking the I2C bus from losing arbitration between repeated start points). Use of this feature results from a trade-off between speed and power consumption of I2C interface. | RW | 0x1 |
0x0: Disables the repeated start operation mode | ||||
0x1: Enables the repeated start operation mode | ||||
3 | HSMODEEN | Enables I2C bus High Speed mode. | RW | 0x1 |
0x0: Disables the I2C high speed mode | ||||
0x1: Enables the I2C high speed mode | ||||
2:0 | HSMCODE | Master code value for I2C High Speed preamble transmission. | RW | 0x0 |
Address Offset | 0x0000 00B8 | ||
Physical Address | 0x4AE0 7DB8 | Instance | DEVICE_PRM |
Description | I2C Interface clock configuration parameters. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HSSCLL | HSSCLH | SCLL | SCLH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | HSSCLL | Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in High-Speed mode of operation. | RW | 0x0 |
23:16 | HSSCLH | Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in High-Speed mode of operation. | RW | 0x0 |
15:8 | SCLL | Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in Fast mode of operation. | RW | 0x0 |
7:0 | SCLH | Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in Fast mode of operation. | RW | 0x0 |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x4AE0 7DBC | Instance | DEVICE_PRM |
Description | Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTUP_COUNT | SLPCNT_VALUE | VSETUPCNT_VALUE | RESERVED | PCHARGECNT_VALUE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | STARTUP_COUNT | Determines the start-up duration of SRAM and ABB LDO. The duration is computed as 16 x NbCycles of system clock cycles. Target is 50us. | RW | 0x78 |
23:16 | SLPCNT_VALUE | Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high. Counting on system clock. Target is 2us. | RW | 0x0 |
15:8 | VSETUPCNT_VALUE | SRAM LDO rampup time from retention to active mode. The duration is computed as 8 x NbCycles of system clock cycles. Target is 30us. | RW | 0x0 |
7:6 | RESERVED | R | 0x0 | |
5:0 | PCHARGECNT_VALUE | Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns. | RW | 0x17 |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x4AE0 7DC0 | Instance | DEVICE_PRM |
Description | Setup of memory in WKUP voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x4AE0 7DC4 | Instance | DEVICE_PRM |
Description | Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIPOFF | ENFUNC5 | ENFUNC4 | ENFUNC3 | ENFUNC2 | ENFUNC1 | ABBOFF_SLEEP | ABBOFF_ACT | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | AIPOFF | Override on AIPOFF input of SRAM LDO. | RW | 0x0 |
0x0: AIPOFF signal is not overriden | ||||
0x1: AIPOFF signal is overriden to '1'. Corresponding SRAM LDO is disabled and in HZ mode. | ||||
7 | ENFUNC5 | ENFUNC5 input of SRAM LDO. | RW | 0x0 |
0x0: Active to retention is a one step transfer | ||||
0x1: Active to retention is a two steps transfer | ||||
6 | ENFUNC4 | ENFUNC4 input of SRAM LDO. | RW | 0x0 |
0x0: One external clock is supplied | ||||
0x1: No external clock is supplied | ||||
5 | ENFUNC3 | ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Sub regulation is disabled | ||||
0x1: Sub regulation is enabled | ||||
4 | ENFUNC2 | ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: External cap is used | ||||
0x1: External cap is not used | ||||
3 | ENFUNC1 | ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Short circuit protection is disabled | ||||
0x1: Short circuit protection is enabled | ||||
2 | ABBOFF_SLEEP | Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
1 | ABBOFF_ACT | Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4AE0 7DC8 | Instance | DEVICE_PRM |
Description | Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_IN_TRANSITION | SRAMLDO_STATUS | RESERVED | RETMODE_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | SRAM_IN_TRANSITION | Status indicating SRAM LDO state machine state. | R | 0x0 |
0x0: SRAM LDO state machine is stable | ||||
0x1: SRAM LDO state machine is in transition state | ||||
8 | SRAMLDO_STATUS | SRAMLDO status | R | 0x0 |
0x0: SRAMLDO is in ACTIVE mode. | ||||
0x1: SRAMLDO is on RETENTION mode. | ||||
7:1 | RESERVED | R | 0x0 | |
0 | RETMODE_ENABLE | Control if the SRAM LDO retention mode is used or not. | R | 0x0 |
0x0: SRAM LDO is not allowed to go to RET mode |
Address Offset | 0x0000 00CC | ||
Physical Address | 0x4AE0 7DCC | Instance | DEVICE_PRM |
Description | Setup of the SRAM LDO for MPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIPOFF | ENFUNC5 | ENFUNC4 | ENFUNC3 | ENFUNC2 | ENFUNC1 | ABBOFF_SLEEP | ABBOFF_ACT | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | AIPOFF | Override on AIPOFF input of SRAM LDO. | RW | 0x0 |
0x0: AIPOFF signal is not overriden | ||||
0x1: AIPOFF signal is overriden to '1'. Corresponding SRAM LDO is disabled and in HZ mode. | ||||
7 | ENFUNC5 | ENFUNC5 input of SRAM LDO. | RW | 0x0 |
0x0: Active to retention is a one step transfer | ||||
0x1: Active to retention is a two steps transfer | ||||
6 | ENFUNC4 | ENFUNC4 input of SRAM LDO. | RW | 0x0 |
0x0: One external clock is supplied | ||||
0x1: No external clock is supplied | ||||
5 | ENFUNC3 | ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Sub regulation is disabled | ||||
0x1: Sub regulation is enabled | ||||
4 | ENFUNC2 | ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: External cap is used | ||||
0x1: External cap is not used | ||||
3 | ENFUNC1 | ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Short circuit protection is disabled | ||||
0x1: Short circuit protection is enabled | ||||
2 | ABBOFF_SLEEP | Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
1 | ABBOFF_ACT | Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 00D0 | ||
Physical Address | 0x4AE0 7DD0 | Instance | DEVICE_PRM |
Description | Control and status of the SRAM LDO for MPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_IN_TRANSITION | SRAMLDO_STATUS | RESERVED | RETMODE_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | SRAM_IN_TRANSITION | Status indicating SRAM LDO state machine state. | R | 0x0 |
0x0: SRAM LDO state machine is stable | ||||
0x1: SRAM LDO state machine is in transition state | ||||
8 | SRAMLDO_STATUS | SRAMLDO status | R | 0x0 |
0x0: SRAMLDO is in ACTIVE mode. | ||||
0x1: SRAMLDO is on RETENTION mode. | ||||
7:1 | RESERVED | R | 0x0 | |
0 | RETMODE_ENABLE | Control if the SRAM LDO retention mode is used or not. | RW | 0x0 |
0x0: SRAM LDO is not allowed to go to RET mode | ||||
0x1: SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET |
Address Offset | 0x0000 00D4 | ||
Physical Address | 0x4AE0 7DD4 | Instance | DEVICE_PRM |
Description | Setup of the SRAM LDO for GPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIPOFF | ENFUNC5 | ENFUNC4 | ENFUNC3 | ENFUNC2 | ENFUNC1 | ABBOFF_SLEEP | ABBOFF_ACT | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | AIPOFF | Override on AIPOFF input of SRAM LDO. | RW | 0x0 |
0x0: AIPOFF signal is not overriden | ||||
0x1: AIPOFF signal is overriden to '1'. Corresponding SRAM LDO is disabled and in HZ mode. | ||||
7 | ENFUNC5 | ENFUNC5 input of SRAM LDO. | RW | 0x0 |
0x0: Active to retention is a one step transfer | ||||
0x1: Active to retention is a two steps transfer | ||||
6 | ENFUNC4 | ENFUNC4 input of SRAM LDO. | RW | 0x0 |
0x0: One external clock is supplied | ||||
0x1: No external clock is supplied | ||||
5 | ENFUNC3 | ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Sub regulation is disabled | ||||
0x1: Sub regulation is enabled | ||||
4 | ENFUNC2 | ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: External cap is used | ||||
0x1: External cap is not used | ||||
3 | ENFUNC1 | ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Short circuit protection is disabled | ||||
0x1: Short circuit protection is enabled | ||||
2 | ABBOFF_SLEEP | Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
1 | ABBOFF_ACT | Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 00D8 | ||
Physical Address | 0x4AE0 7DD8 | Instance | DEVICE_PRM |
Description | Control and status of the SRAM LDO for GPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_IN_TRANSITION | SRAMLDO_STATUS | RESERVED | RETMODE_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | SRAM_IN_TRANSITION | Status indicating SRAM LDO state machine state. | R | 0x0 |
0x0: SRAM LDO state machine is stable | ||||
0x1: SRAM LDO state machine is in transition state | ||||
8 | SRAMLDO_STATUS | SRAMLDO status | R | 0x0 |
0x0: SRAMLDO is in ACTIVE mode. | ||||
0x1: SRAMLDO is on RETENTION mode. | ||||
7:1 | RESERVED | R | 0x0 | |
0 | RETMODE_ENABLE | Control if the SRAM LDO retention mode is used or not. | RW | 0x0 |
0x0: SRAM LDO is not allowed to go to RET mode | ||||
0x1: SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET |
Address Offset | 0x0000 00DC | ||
Physical Address | 0x4AE0 7DDC | Instance | DEVICE_PRM |
Description | Selects the MPU_ABB LDO mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_WTCNT_VALUE | RESERVED | RESERVED | RESERVED | ACTIVE_FBB_SEL | RESERVED | SR2EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:8 | SR2_WTCNT_VALUE | LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive] | RW | 0x0 |
7:5 | RESERVED | R | 0x0 | |
4 | RESERVED | R | 0x0 | |
3 | RESERVED | R | 0x0 | |
2 | ACTIVE_FBB_SEL | Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] | RW | 0x0 |
0x0: ABB LDO is in bypass mode | ||||
0x1: ABB LDO is in FBB mode | ||||
1 | RESERVED | R | 0x0 | |
0 | SR2EN | Enable ABB power management | RW | 0x0 |
0x0: ABB LDO is put in bypass mode | ||||
0x1: ABB LDO will operate accordingly to settings |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4AE0 7DE0 | Instance | DEVICE_PRM |
Description | Control and Status of ABB on MPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_IN_TRANSITION | RESERVED | SR2_STATUS | OPP_CHANGE | OPP_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6 | SR2_IN_TRANSITION | Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. | R | 0x0 |
0x0: IDLE | ||||
0x1: Indicates that VBBLDO_CON is in transition and SR2_STATUS bits are not stable to read. | ||||
5 | RESERVED | R | 0x0 | |
4:3 | SR2_STATUS | Indicate ABB LDO current operation status | R | 0x0 |
0x0: ABB LDO is placed in bypass mode. | ||||
0x1: Reserved | ||||
0x2: ABB LDO is placed in FBB active mode. | ||||
0x3: Reserved | ||||
2 | OPP_CHANGE | When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted. | RW | 0x0 |
1:0 | OPP_SEL | To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to ABB LDO Programming sequence. | RW | 0x0 |
0x0: default : Nominal | ||||
0x1: Fast OPP |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x4AE0 7DE4 | Instance | DEVICE_PRM |
Description | Selects the GPU_ABB LDO mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_WTCNT_VALUE | RESERVED | RESERVED | RESERVED | ACTIVE_FBB_SEL | RESERVED | SR2EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:8 | SR2_WTCNT_VALUE | LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive] | RW | 0x0 |
7:5 | RESERVED | R | 0x0 | |
4 | RESERVED | R | 0x0 | |
3 | RESERVED | R | 0x0 | |
2 | ACTIVE_FBB_SEL | Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] | RW | 0x0 |
0x0: ABB LDO is in bypass mode | ||||
0x1: ABB LDO is in FBB mode | ||||
1 | RESERVED | R | 0x0 | |
0 | SR2EN | Enable ABB power management | RW | 0x0 |
0x0: ABB LDO is put in bypass mode | ||||
0x1: ABB LDO will operate accordingly to settings |
Address Offset | 0x0000 00E8 | ||
Physical Address | 0x4AE0 7DE8 | Instance | DEVICE_PRM |
Description | Control and Status of ABB on GPU voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_IN_TRANSITION | RESERVED | SR2_STATUS | OPP_CHANGE | OPP_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6 | SR2_IN_TRANSITION | Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. | R | 0x0 |
0x0: IDLE | ||||
0x1: Indicates that VBBLDO_CON is in transition and SR2_STATUS bits are not stable to read. | ||||
5 | RESERVED | R | 0x0 | |
4:3 | SR2_STATUS | Indicate ABB LDO current operation status | R | 0x0 |
0x0: ABB LDO is placed in bypass mode. | ||||
0x1: Reserved | ||||
0x2: ABB LDO is placed in FBB active mode. | ||||
0x3: Reserved | ||||
2 | OPP_CHANGE | When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted. | RW | 0x0 |
1:0 | OPP_SEL | To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to ABB LDO Programming sequence. | RW | 0x0 |
0x0: default : Nominal | ||||
0x1: Fast OPP |
Address Offset | 0x0000 00EC | ||
Physical Address | 0x4AE0 7DEC | Instance | DEVICE_PRM |
Description | Setup of the bandgap. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STARTUP_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x0 | |
7:0 | STARTUP_COUNT | Determines the start-up duration of BANDGAP. The duration is computed as 32 x NbCycles of system clock cycles. Target is 100us. | RW | 0x78 |
Address Offset | 0x0000 00F0 | ||
Physical Address | 0x4AE0 7DF0 | Instance | DEVICE_PRM |
Description | This register is used to control device OFF transition. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EMIF2_OFFWKUP_DISABLE | EMIF1_OFFWKUP_DISABLE | RESERVED | DEVICE_OFF_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | EMIF2_OFFWKUP_DISABLE | Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode. [warm reset insensitive] | RW | 0x0 |
0x0: Notifier is activated. | ||||
0x1: Notifier is not activated - stays low | ||||
8 | EMIF1_OFFWKUP_DISABLE | Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode. [warm reset insensitive] | RW | 0x0 |
0x0: Notifier is activated. | ||||
0x1: Notifier is not activated - stays low | ||||
7:1 | RESERVED | R | 0x0 | |
0 | DEVICE_OFF_ENABLE | Controls transition to device OFF mode. | RW | 0x0 |
0x0: Device is not allowed to perform transition to OFF mode | ||||
0x1: Device is allowed to perform transition to OFF mode as soon as all power domains in MPU, MM and CORE voltage are in OFF or OSWRET state (open switch retention) |
Address Offset | 0x0000 00F4 | ||
Physical Address | 0x4AE0 7DF4 | Instance | DEVICE_PRM |
Description | This register stores the start descriptor address of automatic restore phase1. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE1_CNDP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | PHASE1_CNDP | Start descriptor address of automatic restore phase1. Hard-coded to SAR_ROM base address. | R | 0x4a05e000 |
Address Offset | 0x0000 00F8 | ||
Physical Address | 0x4AE0 7DF8 | Instance | DEVICE_PRM |
Description | This register stores the start descriptor address of automatic restore phase2A. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE2A_CNDP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | PHASE2A_CNDP | Start descriptor address of automatic restore phase2A. Hard-coded to SAR_ROM base address + 0x30. | R | 0x4a05e030 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x4AE0 7DFC | Instance | DEVICE_PRM |
Description | This register stores the start descriptor address of automatic restore phase2B. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE2B_CNDP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | PHASE2B_CNDP | Start descriptor address of automatic restore phase2B. Hard-coded to SAR_ROM base address + 0x60. | R | 0x4a05e060 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4AE0 7E00 | Instance | DEVICE_PRM |
Description | This register is used to control dedicated interfaces between on-chip modem and APE. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODEM_SHUTDOWN_IRQ | MODEM_WAKE_IRQ | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | MODEM_SHUTDOWN_IRQ | Controls an interrupt signal to shutdown modem. | RW | 0x0 |
0x0: Interrupt is inactive | ||||
0x1: Interrupt is active | ||||
8 | MODEM_WAKE_IRQ | Controls an interrupt signal to wakeup modem. | RW | 0x0 |
0x0: Interrupt is inactive | ||||
0x1: Interrupt is active | ||||
7:0 | RESERVED | R | 0x0 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4AE0 7E10 | Instance | DEVICE_PRM |
Description | This register provides a status on the current MPU voltage domain state. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTRANSITION | RESERVED | VOLTSTATEST |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:21 | RESERVED | R | 0x0 | |
20 | INTRANSITION | Domain transition status | R | 0x0 |
0x0: No on-going transition on voltage domain | ||||
0x1: Voltage domain transition is in progress. | ||||
19:2 | RESERVED | R | 0x0 | |
1:0 | VOLTSTATEST | Current voltage state status | R | 0x3 |
0x0: Voltage domain is OFF | ||||
0x1: Voltage domain is in RETENTION | ||||
0x2: Voltage domain is SLEEP | ||||
0x3: Voltage domain is ON |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4AE0 7E14 | Instance | DEVICE_PRM |
Description | This register provides a status on the current MM voltage domain state. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTRANSITION | RESERVED | VOLTSTATEST |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:21 | RESERVED | R | 0x0 | |
20 | INTRANSITION | Domain transition status | R | 0x0 |
0x0: No on-going transition on voltage domain | ||||
0x1: Voltage domain transition is in progress. | ||||
19:2 | RESERVED | R | 0x0 | |
1:0 | VOLTSTATEST | Current voltage state status | R | 0x3 |
0x0: Voltage domain is OFF | ||||
0x1: Voltage domain is in RETENTION | ||||
0x2: Voltage domain is SLEEP | ||||
0x3: Voltage domain is ON |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4AE0 7E18 | Instance | DEVICE_PRM |
Description | Setup of the SRAM LDO for DSPEVE voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIPOFF | ENFUNC5 | ENFUNC4 | ENFUNC3 | ENFUNC2 | ENFUNC1 | ABBOFF_SLEEP | ABBOFF_ACT | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | AIPOFF | Override on AIPOFF input of SRAM LDO. | RW | 0x0 |
0x0: AIPOFF signal is not overriden | ||||
0x1: AIPOFF signal is overriden to '1'. Corresponding SRAM LDO is disabled and in HZ mode. | ||||
7 | ENFUNC5 | ENFUNC5 input of SRAM LDO. | RW | 0x0 |
0x0: Active to retention is a one step transfer | ||||
0x1: Active to retention is a two steps transfer | ||||
6 | ENFUNC4 | ENFUNC4 input of SRAM LDO. | RW | 0x0 |
0x0: One external clock is supplied | ||||
0x1: No external clock is supplied | ||||
5 | ENFUNC3 | ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Sub regulation is disabled | ||||
0x1: Sub regulation is enabled | ||||
4 | ENFUNC2 | ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: External cap is used | ||||
0x1: External cap is not used | ||||
3 | ENFUNC1 | ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Short circuit protection is disabled | ||||
0x1: Short circuit protection is enabled | ||||
2 | ABBOFF_SLEEP | Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
1 | ABBOFF_ACT | Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4AE0 7E1C | Instance | DEVICE_PRM |
Description | Setup of the SRAM LDO for IVA voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIPOFF | ENFUNC5 | ENFUNC4 | ENFUNC3 | ENFUNC2 | ENFUNC1 | ABBOFF_SLEEP | ABBOFF_ACT | ENABLE_RTA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | AIPOFF | Override on AIPOFF input of SRAM LDO. | RW | 0x0 |
0x0: AIPOFF signal is not overriden | ||||
0x1: AIPOFF signal is overriden to '1'. Corresponding SRAM LDO is disabled and in HZ mode. | ||||
7 | ENFUNC5 | ENFUNC5 input of SRAM LDO. | RW | 0x0 |
0x0: Active to retention is a one step transfer | ||||
0x1: Active to retention is a two steps transfer | ||||
6 | ENFUNC4 | ENFUNC4 input of SRAM LDO. | RW | 0x0 |
0x0: One external clock is supplied | ||||
0x1: No external clock is supplied | ||||
5 | ENFUNC3 | ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Sub regulation is disabled | ||||
0x1: Sub regulation is enabled | ||||
4 | ENFUNC2 | ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: External cap is used | ||||
0x1: External cap is not used | ||||
3 | ENFUNC1 | ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: Short circuit protection is disabled | ||||
0x1: Short circuit protection is enabled | ||||
2 | ABBOFF_SLEEP | Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
1 | ABBOFF_ACT | Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: SRAMNWA supplied with VDDS | ||||
0x1: SRAMNWA supplied with VDDAR | ||||
0 | ENABLE_RTA | Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this. | RW | 0x0 |
0x0: HD memory RTA feature is disabled | ||||
0x1: HD memory RTA feature is enabled |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4AE0 7E20 | Instance | DEVICE_PRM |
Description | Control and Status of ABB on DSPEVE voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_IN_TRANSITION | RESERVED | SR2_STATUS | OPP_CHANGE | OPP_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6 | SR2_IN_TRANSITION | Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. | R | 0x0 |
0x0: IDLE | ||||
0x1: Indicates that VBBLDO_CON is in transition and SR2_STATUS bits are not stable to read. | ||||
5 | RESERVED | R | 0x0 | |
4:3 | SR2_STATUS | Indicate ABB LDO current operation status | R | 0x0 |
0x0: ABB LDO is placed in bypass mode. | ||||
0x1: Reserved | ||||
0x2: ABB LDO is placed in FBB active mode. | ||||
0x3: Reserved | ||||
2 | OPP_CHANGE | When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted. | RW | 0x0 |
1:0 | OPP_SEL | To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to ABB LDO Programming sequence. | RW | 0x0 |
0x0: default : Nominal | ||||
0x1: Fast OPP |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4AE0 7E24 | Instance | DEVICE_PRM |
Description | Control and Status of ABB on IVA voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_IN_TRANSITION | RESERVED | SR2_STATUS | OPP_CHANGE | OPP_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6 | SR2_IN_TRANSITION | Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. | R | 0x0 |
0x0: IDLE | ||||
0x1: Indicates that VBBLDO_CON is in transition and SR2_STATUS bits are not stable to read. | ||||
5 | RESERVED | R | 0x0 | |
4:3 | SR2_STATUS | Indicate ABB LDO current operation status | R | 0x0 |
0x0: ABB LDO is placed in bypass mode. | ||||
0x1: Reserved | ||||
0x2: ABB LDO is placed in FBB active mode. | ||||
0x3: Reserved | ||||
2 | OPP_CHANGE | When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted. | RW | 0x0 |
1:0 | OPP_SEL | To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to ABB LDO Programming sequence. | RW | 0x0 |
0x0: default : Nominal | ||||
0x1: Fast OPP |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4AE0 7E28 | Instance | DEVICE_PRM |
Description | Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_IN_TRANSITION | SRAMLDO_STATUS | RESERVED | RETMODE_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | SRAM_IN_TRANSITION | Status indicating SRAM LDO state machine state. | R | 0x0 |
0x0: SRAM LDO state machine is stable | ||||
0x1: SRAM LDO state machine is in transition state | ||||
8 | SRAMLDO_STATUS | SRAMLDO status | R | 0x0 |
0x0: SRAMLDO is in ACTIVE mode. | ||||
0x1: SRAMLDO is on RETENTION mode. | ||||
7:1 | RESERVED | R | 0x0 | |
0 | RETMODE_ENABLE | Control if the SRAM LDO retention mode is used or not. | RW | 0x0 |
0x0: SRAM LDO is not allowed to go to RET mode | ||||
0x1: SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4AE0 7E2C | Instance | DEVICE_PRM |
Description | Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_IN_TRANSITION | SRAMLDO_STATUS | RESERVED | RETMODE_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9 | SRAM_IN_TRANSITION | Status indicating SRAM LDO state machine state. | R | 0x0 |
0x0: SRAM LDO state machine is stable | ||||
0x1: SRAM LDO state machine is in transition state | ||||
8 | SRAMLDO_STATUS | SRAMLDO status | R | 0x0 |
0x0: SRAMLDO is in ACTIVE mode. | ||||
0x1: SRAMLDO is on RETENTION mode. | ||||
7:1 | RESERVED | R | 0x0 | |
0 | RETMODE_ENABLE | Control if the SRAM LDO retention mode is used or not. | RW | 0x0 |
0x0: SRAM LDO is not allowed to go to RET mode | ||||
0x1: SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4AE0 7E30 | Instance | DEVICE_PRM |
Description | Selects the GPU_ABB LDO mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_WTCNT_VALUE | RESERVED | RESERVED | RESERVED | ACTIVE_FBB_SEL | RESERVED | SR2EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:8 | SR2_WTCNT_VALUE | LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive] | RW | 0x0 |
7:5 | RESERVED | R | 0x0 | |
4 | RESERVED | R | 0x0 | |
3 | RESERVED | R | 0x0 | |
2 | ACTIVE_FBB_SEL | Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] | RW | 0x0 |
0x0: ABB LDO is in bypass mode | ||||
0x1: ABB LDO is in FBB mode | ||||
1 | RESERVED | R | 0x0 | |
0 | SR2EN | Enable ABB power management | RW | 0x0 |
0x0: ABB LDO is put in bypass mode | ||||
0x1: ABB LDO will operate accordingly to settings |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4AE0 7E34 | Instance | DEVICE_PRM |
Description | Selects the GPU_ABB LDO mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SR2_WTCNT_VALUE | RESERVED | RESERVED | RESERVED | ACTIVE_FBB_SEL | RESERVED | SR2EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:8 | SR2_WTCNT_VALUE | LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive] | RW | 0x0 |
7:5 | RESERVED | R | 0x0 | |
4 | RESERVED | R | 0x0 | |
3 | RESERVED | R | 0x0 | |
2 | ACTIVE_FBB_SEL | Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] | RW | 0x0 |
0x0: ABB LDO is in bypass mode | ||||
0x1: ABB LDO is in FBB mode | ||||
1 | RESERVED | R | 0x0 | |
0 | SR2EN | Enable ABB power management | RW | 0x0 |
0x0: ABB LDO is put in bypass mode | ||||
0x1: ABB LDO will operate accordingly to settings |