SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Table 4-3 lists the DMM registers that are duplicated locally in the MPU_MA. These registers have the same names except that DMM is replaced by MPU_MA. Software must keep the content of these registers equal to the content of their counterparts in the DMM.
Register | Type | Width (Bits) | Base Address |
---|---|---|---|
MA_LISA_LOCK | RW | 32 | 0x482A F01C |
MA_LISA_MAP_i (where i = 0 to 3) | RW | 32 | 0x482A F040–0x482A F04C |
For descriptions of the registers, see Section 15.2, Dynamic Memory Manager. The only differences are the following reset values of the MA_LISA_MAP_0 register:
The configuration of the MPU_MA must be programmed by the Cortex-A15 MPU to match the configuration of the DMM during boot. The registers must be locked after initial programming to avoid corruption by application software. When the SM configuration registers are being programmed, there are no interlocks or safeguards to prevent accesses from being processed at the same time. The MA_LISA_LOCK and MA_LISA_MAP_i registers are retained during power down of retention mode.
If an access is made to a region marked as having unused address space or an unmapped SDRC map, no access is made to the EMIF and an error is returned. If an access is made to a region marked as accesses-SDRC-internal-registers, no access occurs to the EMIF and an error is returned. This is because the internal registers are not accessible from this port.
If an access is made to a region that is not mapped to any LISA section, or selects a section with one of the following programmations, then no access is made to the EMIF and an error is returned on the AXI port: