SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
This section describes the interrupt events that can trigger the CAL_IRQ signal (see also Section 8.3.1, CAL Main Integration Attributes).
The CAL does not provide an event to detect Attribute Payload data at low level protocol level. Attribute data can only be sent to memory and therefore software can use the IRQ_WDMA_START / END events detected by the Write DMA block.
Table 8-6 lists the event generation and corresponding registers of the CSI2 Low Level Protocol engines.
Event and Register | Description |
---|---|
CAL_CSI2_COMPLEXIO_IRQENABLE_l[27] FIFO_OVF_IRQ | FIFO overflow error: This interrupt is triggered when a FIFO overflow is detected. An overflow can occur if there is a mismatch between the data input and output rates. In case of an overflow the module properly finishes the burst that has been started and does not issue any new OCP transactions on the master port. A reset of the module is required to restart correctly. |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[28] SHORT_PACKET_IRQ | Short packet reception (other than sync events: line start, line end, frame start, and frame end; only data types from 0x8 to 0xF are considered) |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[30] ECC_NO_CORRECTION_IRQ | ECC was not used to correct the header because the error is larger than 1 bit (short and long packets). |
CAL_CSI2_VC_IRQENABLE_l[] ECC_CORRECTION_IRQ_x, where x = [0...3] | ECC was used to correct a 1-bit error (short packet only). |
CAL_CSI2_VC_IRQENABLE_l[] FS_IRQ_x, where x = [0...3] | Frame start: This interrupt is triggered when a frame-start synchronization code is detected in the CSI2 data stream. |
CAL_CSI2_VC_IRQENABLE_l[] FE_IRQ_x, where x = [0...3] | Frame end: This interrupt is triggered when a frame-end synchronization code is detected in the CSI2 data stream. |
CAL_CSI2_VC_IRQENABLE_l[] LS_IRQ_x, where x = [0...3] | Line start: This interrupt is triggered when a line-start synchronization code is detected in the CSI2 data stream. |
CAL_CSI2_VC_IRQENABLE_l[] LE_IRQ_x, where x = [0...3] | Line end: This interrupt is triggered when a line-end synchronization code is detected in the CSI2 data stream. |
CAL_CSI2_VC_IRQENABLE_l[] CS_IRQ_x, where x = [0...3] | CS error: This interrupt is triggered when a mismatch between the transmitter and receiver checksums (payload) is detected. |
Table 8-7 lists CSI2 Complex I/O event generation. The events are checked and controlled from the CAL_CSI2_COMPLEXIO_IRQSTATUS_l and CAL_CSI2_COMPLEXIO_IRQENABLE_l registers.
Event and Register | Description |
---|---|
CAL_CSI2_COMPLEXIO_IRQENABLE_l[0] ERRSOTHS1 | Start of transmission error for lane 1 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[1] ERRSOTHS2 | Start of transmission error for lane 2 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[2] ERRSOTHS3 | Start of transmission error for lane 3 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[3] ERRSOTHS3 | Start of transmission error for lane 4 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[4] ERRSOTHS3 | Start of transmission error for lane 5 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[5] ERRSOTSYNCHS1 | Start of transmission sync error for lane 1 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[6] ERRSOTSYNCHS2 | Start of transmission sync error for lane 2 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[7] ERRSOTSYNCHS3 | Start of transmission sync error for lane 3 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[8] ERRSOTSYNCHS3 | Start of transmission sync error for lane 4 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[9] ERRSOTSYNCHS3 | Start of transmission sync error for lane 5 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[10] ERRESC1 | Escape entry error for lane 1 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[11] ERRESC2 | Escape entry error for lane 2 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[12] ERRESC3 | Escape entry error for lane 3 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[13] ERRESC4 | Escape entry error for lane 4 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[14] ERRESC5 | Escape entry error for lane 5 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[15] ERRCONTROL1 | Control error for lane 1 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[16] ERRCONTROL2 | Control error for lane 2 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[17] ERRCONTROL3 | Control error for lane 3 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[18] ERRCONTROL4 | Control error for lane 4 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[19] ERRCONTROL5 | Control error for lane 5 |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[20] STATEULPM1 | Lane 1 in ULPM |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[21] STATEULPM2 | Lane 2 in ULPM |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[22] STATEULPM3 | Lane 3 in ULPM |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[23] STATEULPM4 | Lane 4 in ULPM |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[24] STATEULPM5 | Lane 5 in ULPM |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[25] STATEALLULPMENTER | All active lanes are entering the ULPM. |
CAL_CSI2_COMPLEXIO_IRQENABLE_l[26] STATEALLULPMEXIT | At least one active lane exited the ULPM. |
Event | Description |
---|---|
IRQ_WDMA_STARTx x= [0 ... CAL_HL_HWINFO[18:13] WCTX - 1] | Frame start. Triggered by the Write DMA when a data word tagged as ATT_HDR_S, ATT_DAT_S, CTRL_HDR_S, PIX_HDR_S or PIX_DAT_FS has been detected by the Write DMA. Typically used by SW to detect when shadowed registers can be updated for the next frame. Refer to Section 8.4.6.8, CAL Write DMA, for more details. |
IRQ_WDMA_ENDx x= [0 ... CAL_HL_HWINFO[18:13] WCTX - 1] | Frame end. Triggered by the Write DMA when the FE tag has been received by the cropping stage and the last data of the last line has been sent to memory. Therefore, this event may be triggered after the last data has been written to memory when data has been discarded by the cropping feature. The FE corresponds to a data word tagged as ATT_HDR_E, ATT_DAT_E, CTRL_HDR_E, PIX_HDR_E, PIX_DAT_FE or FE_CODE. Typically used by SW to detect when all data of a header, attribute packet, control packet or pixel frame has been written to memory. This event is triggered when the last OCP transaction has been sent to memory but before the response for this OCP transaction has been received from the target. Therefore, there is a small delay between the moment where the event is triggered and the last data can be read back from the buffer. Typically that delay is compensated by IRQ detection latencies. |
IRQ_WDMA_CIRCx x= [0 ... CAL_HL_HWINFO[18:13] WCTX - 1] | Circular event. Triggered when the number of lines defined by CAL_WR_DMA_OFST_k[23:22] CIRC_MODE has been sent to the OCP master port. |
Event | Description |
---|---|
IRQ_LINE_NUMBER | Line number reached. The line number programmed in CAL_LINE_NUMBER_EVT[29:16] LINE register bit-field) is received on CPORT# CAL_LINE_NUMBER_EVT[4:0] CPORT. |
Event | Description |
---|---|
IRQ_VPORT_EOF | Event triggered when data tagged as PIX_DAT_FE is sent to the video port . Typically used by SW to detect when all data has been sent to the video port. |
On CAL top level, the different events trigger IRQs, if they have been enabled using the CAL_HL_IRQENABLE_SET_j register. The status can be read from the CAL_HL_IRQSTATUS_j register. The event-to-register mapping is shown in Figure 8-4.
CAL_HL_IRQSTATUS_j does not refer to events, but is used to collect events tracked in CAL_CSI2_VC_IRQSTATUS_l and CAL_CSI2_COMPLEXIO_IRQSTATUS_l registers, and enabled by CAL_CSI2_VC_IRQENABLE_l and CAL_CSI2_COMPLEXIO_IRQENABLE_l registers. SW must use them to detect, if a Complex I/O or PPI event is pending and then get event details from the relevant second level IRQ status register. SW must only clear those events by setting the relevant bits in the CAL_CSI2_VC_IRQSTATUS_l and CAL_CSI2_COMPLEXIO_IRQSTATUS_l registers. CAL_HL_IRQSTATUS_j is automatically cleared by the HW when no more enabled Complex I/O or PPI events are pending