SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4880 4000 | Instance | OCMC_RAM1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | TI internal data | R | 0x- |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4880 4004 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:4 | RESERVED | R | 0x0 | |
3:2 | IDLEMODE | Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. | RW | 0x2 |
0x0: Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. | ||||
0x1: No-idle mode: local target never enters idle state. Backup mode, for debug only | ||||
0x2: Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate IRQ-request-related wakeup events. | ||||
0x3: Smart-idle wakeup-capable mode: local target’s idle state eventually follows (acknowledges) the system’s idle requests, depending on the IP module’s internal requirements. IP module may generate IRQ-request-related wakeup events when in idle state. | ||||
1:0 | RESERVED | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4880 4008 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SW_RST |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | SW_RST | Software reset of the OCM controller configuration and history logic (does not reset L4 interface) | RW | 0x0 |
0x0: Normal operation (OCM controller is not reset) | ||||
0x1: Reset the OCM controller (except its registers). This bit must be set back to 0x0 to resume the normal operation of the OCM Controller. |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4880 400C | Instance | OCMC_RAM1 |
Description | This register provides the status of the OCM Controller configuration. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VBUF_ADDR_MSB | RESERVED | MEM_CBUF_ENABLE | MEM_ECC_ENABLE | RESERVED | MEM_SIZE_128K_CNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:17 | RESERVED | R | 0x0 | |
16:12 | VBUF_ADDR_MSB | This bit field returns the MSB bit of the valid VBUF address range. The default value of 23 means that the valid VBUF address range is from 0x8000 0000 to 0x80FF FFFF | R | 0x- |
11:10 | RESERVED | R | 0x0 | |
9 | MEM_CBUF_ENABLE | Indicates whether CBUF is supported or not. | R | 0x- |
0x0: CBUF not supported | ||||
0x1: CBUF supported | ||||
8 | MEM_ECC_ENABLE | Indicates whether ECC is supported or not. | R | 0x- |
0x0: ECC not supported | ||||
0x1: ECC supported | ||||
7:5 | RESERVED | R | 0x0 | |
4:0 | MEM_SIZE_128K_CNT | This bit field indicates how many 128KiB memory blocks are present in the SRAM. Access beyond the memory size reported in the MEM_SIZE_128K_CNT bit field results in an address error interrupt. 0x1: One 128KiB memory block 0x2: Two 128KiB memory blocks ... 0x14: 20 memory blocks of 128KiB | R | 0x- |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4880 4040 | Instance | OCMC_RAM1 |
Description | This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame. | RW | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
2 | ADDR_ERR_FOUND | RW | 0x0 | |
1 | DED_ERR_FOUND | RW | 0x0 | |
0 | SEC_ERR_FOUND | RW | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4880 4044 | Instance | OCMC_RAM1 |
Description | Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW W1toClr | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW W1toClr | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW W1toClr | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW W1toClr | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW W1toClr | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW W1toClr | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
2 | ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
1 | DED_ERR_FOUND | RW W1toClr | 0x0 | |
0 | SEC_ERR_FOUND | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4880 4048 | Instance | OCMC_RAM1 |
Description | Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
2 | ADDR_ERR_FOUND | RW | 0x0 | |
1 | DED_ERR_FOUND | RW | 0x0 | |
0 | SEC_ERR_FOUND | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4880 404C | Instance | OCMC_RAM1 |
Description | Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW W1toClr | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW W1toClr | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW W1toClr | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW W1toClr | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW W1toClr | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW W1toClr | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
2 | ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
1 | DED_ERR_FOUND | RW W1toClr | 0x0 | |
0 | SEC_ERR_FOUND | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4880 4050 | Instance | OCMC_RAM1 |
Description | This register contains the EOI vector. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | EOI_VECTOR | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4880 4060 | Instance | OCMC_RAM1 |
Description | This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
2 | ADDR_ERR_FOUND | RW | 0x0 | |
1 | DED_ERR_FOUND | RW | 0x0 | |
0 | SEC_ERR_FOUND | RW | 0x0 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4880 4064 | Instance | OCMC_RAM1 |
Description | Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW W1toClr | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW W1toClr | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW W1toClr | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW W1toClr | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW W1toClr | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW W1toClr | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
2 | ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
1 | DED_ERR_FOUND | RW W1toClr | 0x0 | |
0 | SEC_ERR_FOUND | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4880 4068 | Instance | OCMC_RAM1 |
Description | Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW | 0x0 | |
2 | ADDR_ERR_FOUND | RW | 0x0 | |
1 | DED_ERR_FOUND | RW | 0x0 | |
0 | SEC_ERR_FOUND | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4880 406C | Instance | OCMC_RAM1 |
Description | Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF_UNDERFLOW_ERR_FOUND | CBUF_OVERFLOW_WRAP_ERR_FOUND | CBUF_OVERFLOW_MID_ERR_FOUND | CBUF_READ_SEQUENCE_ERR_FOUND | CBUF_VBUF_READ_START_ERR_FOUND | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | CBUF_WRITE_SEQUENCE_ERR_FOUND | CBUF_VBUF_WRITE_START_ERR_FOUND | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | CBUF_VIRTUAL_ADDR_ERR_FOUND | OUT_OF_RANGE_ERR_FOUND | ADDR_ERR_FOUND | DED_ERR_FOUND | SEC_ERR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14 | CBUF_SHORT_FRAME_DETECT_FOUND | CBUF detected short frame | RW W1toClr | 0x0 |
13 | CBUF_UNDERFLOW_ERR_FOUND | RW W1toClr | 0x0 | |
12 | CBUF_OVERFLOW_WRAP_ERR_FOUND | RW W1toClr | 0x0 | |
11 | CBUF_OVERFLOW_MID_ERR_FOUND | RW W1toClr | 0x0 | |
10 | CBUF_READ_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
9 | CBUF_VBUF_READ_START_ERR_FOUND | RW W1toClr | 0x0 | |
8 | CBUF_READ_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
7 | CBUF_WRITE_SEQUENCE_ERR_FOUND | RW W1toClr | 0x0 | |
6 | CBUF_VBUF_WRITE_START_ERR_FOUND | RW W1toClr | 0x0 | |
5 | CBUF_WR_OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
4 | CBUF_VIRTUAL_ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
3 | OUT_OF_RANGE_ERR_FOUND | RW W1toClr | 0x0 | |
2 | ADDR_ERR_FOUND | RW W1toClr | 0x0 | |
1 | DED_ERR_FOUND | RW W1toClr | 0x0 | |
0 | SEC_ERR_FOUND | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4880 4070 | Instance | OCMC_RAM1 |
Description | This register contains the EOI vector. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | EOI_VECTOR | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4880 4080 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CFG_ECC_OPT_NON_ECC_READ | CFG_ECC_ERR_SRESP_EN | CFG_ECC_SEC_AUTO_CORRECT | CFG_OCMC_MODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x0 | |
5 | CFG_ECC_OPT_NON_ECC_READ | Optimize read latency for non-ECC read. Returns the data one cycle faster if the read access is from a non-ECC enabled space. 0x0: Disable 0x1: Enable | RW | 0x0 |
4 | CFG_ECC_ERR_SRESP_EN | ECC non-correctable error SRESP enable. Enables ERR return on L3 OCP SRESP when a non-correctable data (DED) or address error is detected. 0x0: Disable 0x1: Enable | RW | 0x0 |
3 | CFG_ECC_SEC_AUTO_CORRECT | SEC error auto correction mode. Enables the OCM Controller to automatically update the wrong data word with the corrected word. 0x0: Disable 0x1: Enable (If the OCM Controller is performing a read-modify operation for a sub-128b write to an ECC enabled memory, the error found during the read phase will be corrected always regardless of the value of this bit) | RW | 0x0 |
2:0 | CFG_OCMC_MODE | OCM Controller memory access modes. 0x0: Non-ECC mode (data access) 0x1: Non-ECC mode (code access) 0x2: Full ECC enabled mode 0x3: Block ECC enabled mode 0x4-0x7: Reserved (internally defaults to 0x0 mode) | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4880 4084 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CFG_ECC_ENABLED_128K_BLK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | CFG_ECC_ENABLED_128K_BLK | ECC memory block enable bits. The active level of each bit is 0x1. Bit [0] -> Address offset range 0x0 to 0x1FFFF Bit [1] -> Address offset range 0x20000 to 0x3FFFF ... Bit [19] -> Address offset range 0x260000 to 0x27FFFF | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4880 4088 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CFG_DISCARD_DUP_ADDR | CFG_ADDR_ERR_CNT_MAX | CFG_DED_CNT_MAX | CFG_SEC_CNT_MAX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:25 | RESERVED | R | 0x0 | |
24 | CFG_DISCARD_DUP_ADDR | Do not save duplicate error address. This bit applies to the SEC, DED and ADDRERR FIFOs. 0x0: Save the duplicated addresses 0x1: Save only the unique addresses | RW | 0x0 |
23:20 | CFG_ADDR_ERR_CNT_MAX | Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt). | RW | 0x1 |
19:16 | CFG_DED_CNT_MAX | Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt). | RW | 0x1 |
15:0 | CFG_SEC_CNT_MAX | Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt). | RW | 0x1 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4880 408C | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEAR_SEC_BIT_DISTR | CLEAR_ADDR_ERR_CNT | CLEAR_DED_ERR_CNT | CLEAR_SEC_ERR_CNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:4 | RESERVED | R | 0x0 | |
3 | CLEAR_SEC_BIT_DISTR | Clear stored single error correction (SEC) bit distribution history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Cleares the following registers: | RW | 0x0 |
2 | CLEAR_ADDR_ERR_CNT | Clear stored address error history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the STATUS_ERROR_CNT[23:20] ADDR_ERROR_CNT bit field and the ADDRERR FIFO | RW | 0x0 |
1 | CLEAR_DED_ERR_CNT | Clear stored double error detection (DED) history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the STATUS_ERROR_CNT[19:16] DED_ERROR_CNT bit field and the DED FIFO | RW | 0x0 |
0 | CLEAR_SEC_ERR_CNT | Clear stored single error correction history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the STATUS_ERROR_CNT[15:0] SEC_ERROR_CNT bit field and the SEC FIFO | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4880 4090 | Instance | OCMC_RAM1 |
Description | OCM Controller error status | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR_ERROR_CNT | DED_ERROR_CNT | SEC_ERROR_CNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23:20 | ADDR_ERROR_CNT | Counter for the address errors found. This bit field is reset when 0x1 is written to the CFG_OCMC_ECC_CLEAR_HIST[2] CLEAR_ADDR_ERR_CNT bit. | R | 0x0 |
19:16 | DED_ERROR_CNT | Counter for the double error detections. This bit field is reset when 0x1 is written to the CFG_OCMC_ECC_CLEAR_HIST[1] CLEAR_DED_ERR_CNT bit. | R | 0x0 |
15:0 | SEC_ERROR_CNT | Counter for the single errors occured. This bit field is reset when 0x1 is written to the CFG_OCMC_ECC_CLEAR_HIST[0] CLEAR_SEC_ERR_CNT bit. | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4880 4094 | Instance | OCMC_RAM1 |
Description | SEC error 128-bit memory address | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALID | ADDRESS_128BIT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:19 | RESERVED | R | 0x0 | |
18 | VALID | SEC FIFO valid addres indication. | R | 0x0 |
0x0: The SEC FIFO is empty | ||||
0x1: There is a valid address in the SEC FIFO | ||||
17:0 | ADDRESS_128BIT | SEC error 128-bit memory address (Read from the SEC error address trace fifo) | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4880 4098 | Instance | OCMC_RAM1 |
Description | DED error 128-bit memory address | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALID | ADDRESS_128BIT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:19 | RESERVED | R | 0x0 | |
18 | VALID | DED FIFO valid addres indication. 0x0: The DED FIFO is empty 0x1: There is a valid address in the DED FIFO | R | 0x0 |
17:0 | ADDRESS_128BIT | DED error 128-bit memory address (Read from the DED error address trace fifo) | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4880 409C | Instance | OCMC_RAM1 |
Description | ADDR error 128-bit memory address | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALID | ADDRESS_128BIT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:19 | RESERVED | R | 0x0 | |
18 | VALID | ADDRERR FIFO valid addres indication. 0x0: The ADDRERR FIFO is empty 0x1: There is a valid address in the ADDRERR FIFO | R | 0x0 |
17:0 | ADDRESS_128BIT | ADDR error 128-bit memory address (Read from the ADDR error address trace fifo) | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4880 40A0 | Instance | OCMC_RAM1 |
Description | SEC data error bit distribution status [31:0] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEC_BIT_ERROR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | SEC_BIT_ERROR_FOUND | 1 in a bit position means that an SEC error was found at that bit position and corrected | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4880 40A4 | Instance | OCMC_RAM1 |
Description | SEC data error bit distribution status [63:32] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEC_BIT_ERROR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | SEC_BIT_ERROR_FOUND | 1 in a bit position means that an SEC error was found at that bit position and corrected | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4880 40A8 | Instance | OCMC_RAM1 |
Description | SEC data error bit distribution status [95:64] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEC_BIT_ERROR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | SEC_BIT_ERROR_FOUND | 1 in a bit position means that an SEC error was found at that bit position and corrected | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4880 40AC | Instance | OCMC_RAM1 |
Description | SEC data error bit distribution status [127:96] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEC_BIT_ERROR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | SEC_BIT_ERROR_FOUND | 1 in a bit position means that an SEC error was found at that bit position and corrected | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4880 40B0 | Instance | OCMC_RAM1 |
Description | SEC ecc code error bit distribution status [7:0] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEC_ECC_CODE_ERROR_FOUND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x0 | |
7:0 | SEC_ECC_CODE_ERROR_FOUND | ECC Code (excluding the parity bit) error distribution [7:0]. For each bit: 0x0: SEC error not found 0x1: SEC error found In the corresponding bit location | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4880 4200 | Instance | OCMC_RAM1 |
Description | CBUF mode enable register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_EN_11 | CBUF_EN_10 | CBUF_EN_9 | CBUF_EN_8 | CBUF_EN_7 | CBUF_EN_6 | CBUF_EN_5 | CBUF_EN_4 | CBUF_EN_3 | CBUF_EN_2 | CBUF_EN_1 | CBUF_EN_0 | RESERVED | NEW_FRAME_SEL | CBUF_DEBUG_EN | CBUF_MODE_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27 | CBUF_EN_11 | CBUF 11 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
26 | CBUF_EN_10 | CBUF 10 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
25 | CBUF_EN_9 | CBUF 9 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
24 | CBUF_EN_8 | CBUF 8 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
23 | CBUF_EN_7 | CBUF 7 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
22 | CBUF_EN_6 | CBUF 6 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
21 | CBUF_EN_5 | CBUF 5 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
20 | CBUF_EN_4 | CBUF 4 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
19 | CBUF_EN_3 | CBUF 3 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
18 | CBUF_EN_2 | CBUF 2 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
17 | CBUF_EN_1 | CBUF 1 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
16 | CBUF_EN_0 | CBUF 0 enable. 0x0: Disable 0x1: Enable | RW | 0x0 |
15:3 | RESERVED | R | 0x0 | |
2 | NEW_FRAME_SEL | CBUF New Frame Event Definition Select. 0x0: New frame event flag is set when a VBUF access is made to the base address of the VBUF 0x1: New frame event flag is set when a VBUF access is made to the base CBUF slice address range of the VBUF | RW | 0x0 |
1 | CBUF_DEBUG_EN | CBUF Debug Enable Mode. 0x0: Default Normal mode. All CBUF accesses with MReqDebug=1 are rejected. 0x1: Debug mode. MReqDebug Interconnect qualifier is ignored. | RW | 0x0 |
0 | CBUF_MODE_EN | CBUF Mode Enable. 0x0: Disable all CBUF address translation 0x1: Enable CBUF address translation | RW | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4880 4204 | Instance | OCMC_RAM1 |
Description | Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic. Sliding CBUF frame tracking will be cleared so that the CBUF now points to the base of the virtual frame buffer. Normally, a reset is not required since the CBUF logic will clear itself when a VBUF access is to the base of the virtual frame. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_RESET_11 | CBUF_RESET_10 | CBUF_RESET_9 | CBUF_RESET_8 | CBUF_RESET_7 | CBUF_RESET_6 | CBUF_RESET_5 | CBUF_RESET_4 | CBUF_RESET_3 | CBUF_RESET_2 | CBUF_RESET_1 | CBUF_RESET_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11 | CBUF_RESET_11 | cbuf_reset_11 | RW W1toClr | 0x0 |
10 | CBUF_RESET_10 | cbuf_reset_10 | RW W1toClr | 0x0 |
9 | CBUF_RESET_9 | cbuf_reset_9 | RW W1toClr | 0x0 |
8 | CBUF_RESET_8 | cbuf_reset_8 | RW W1toClr | 0x0 |
7 | CBUF_RESET_7 | cbuf_reset_7 | RW W1toClr | 0x0 |
6 | CBUF_RESET_6 | cbuf_reset_6 | RW W1toClr | 0x0 |
5 | CBUF_RESET_5 | cbuf_reset_5 | RW W1toClr | 0x0 |
4 | CBUF_RESET_4 | cbuf_reset_4 | RW W1toClr | 0x0 |
3 | CBUF_RESET_3 | cbuf_reset_3 | RW W1toClr | 0x0 |
2 | CBUF_RESET_2 | cbuf_reset_2 | RW W1toClr | 0x0 |
1 | CBUF_RESET_1 | cbuf_reset_1 | RW W1toClr | 0x0 |
0 | CBUF_RESET_0 | cbuf_reset_0 | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0208 | ||
Physical Address | 0x4880 4208 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UNDERFLOW_LAST_CBUF_SLICE_DISABLE | OVERFLOW_CHECK_REENABLE_SEL | OVERFLOW_WRITE_HANDLER_SEL | UNDERFLOW_ERR_CHECK_EN | OVERFLOW_ERR_CHECK_EN | SHORT_FRAME_PREV_EOF_SEL | SHORT_FRAME_DETECT_CHECK_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | UNDERFLOW_LAST_CBUF_SLICE_DISABLE | 0x0: Check underflow even when read is from the last CBUF slice 0x1: Disable underflow check when read is from the last CBUF slice | RW | 0x0 |
7:6 | OVERFLOW_CHECK_REENABLE_SEL | Overflow check re-enable selection. 0x0: Overflow check is disabled until next wtire to or read from virtual frame start address is detected 0x1: Overflow check is disabled until next write to virtual frame start address is detected 0x2: Overflow check is disabled until next read from virtual frame start address is detected 0x3: Overflow check is re-enabled immediately | RW | 0x0 |
5:4 | OVERFLOW_WRITE_HANDLER_SEL | Overflow write handler selection. 0x0: Writes disabled only on CBUF_overflow_wrap cases until next write to virtual frame start address is detected 0x1: Writes disabled on all overflow cases until next write to virtual frame start address is detected 0x2: Writes serviced with CBUF pointer updated even on overflow condition 0x3: Reserved | RW | 0x0 |
3 | UNDERFLOW_ERR_CHECK_EN | Underflow chek enable. | RW | 0x0 |
0x0: Underflow check enabled | ||||
0x1: Underflow check disabled | ||||
2 | OVERFLOW_ERR_CHECK_EN | Overflow chek enable. | RW | 0x0 |
0x0: Overflow check enabled | ||||
0x1: Overflow check disabled | ||||
1 | SHORT_FRAME_PREV_EOF_SEL | 0x0: previous frame EOF history is set if the last write address is equal to the VBUF frame end address 0x1: previous frame EOF history is set if the last write address is in the Last CBUF slice | RW | 0x0 |
0 | SHORT_FRAME_DETECT_CHECK_EN | Short frame detection enable. | RW | 0x0 |
0x0: Detection enabled | ||||
0x1: Detection disabled |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 020C | ||
Physical Address | 0x4880 420C | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | Indicates that the CBUF write address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x4880 4210 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF write is not to the base address at vbuf access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x4880 4214 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x4880 4218 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | Indicates that the CBUF read address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 021C | ||
Physical Address | 0x4880 421C | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF read is not from the base address at VBUF access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0220 | ||
Physical Address | 0x4880 4220 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF read address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0224 | ||
Physical Address | 0x4880 4224 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF overflow condition detected in the middle of a frame. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0228 | ||
Physical Address | 0x4880 4228 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF overflow condition detected during buffer switching. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 022C | ||
Physical Address | 0x4880 422C | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF underflow condition detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0230 | ||
Physical Address | 0x4880 4230 | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBUF_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | CBUF_ERR | CBUF short frame detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set. | RW W1toClr | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0240 + (i*16); i = 0 to 11 | ||
Physical Address | 0x4880 4240 + (i*16) | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | The virtual address range is determined by the OCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1. | R | 0x80 |
23:4 | ADDR | Virtual frame start address for this CBUF - bits [23:4] | RW | 0x0 |
3:0 | RESERVED | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0244 + (i*16); i = 0 to 11 | ||
Physical Address | 0x4880 4244 + (i*16) | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | The virtual address range is determined by the OCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1. | R | 0x80 |
23:4 | ADDR | Virtual frame end address for this CBUF - bits [23:4] | RW | 0x0 |
3:0 | RESERVED | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0248 + (i*16); i = 0 to 11 | ||
Physical Address | 0x4880 4248 + (i*16) | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:22 | RESERVED | R | 0x0 | |
21:4 | ADDR | SRAM start address for this CBUF - bits [21:4] | RW | 0x0 |
3:0 | RESERVED | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 024C + (i*16); i = 0 to 11 | ||
Physical Address | 0x4880 424C + (i*16) | Instance | OCMC_RAM1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUF_SIZE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:4 | BUF_SIZE | SRAM size allocated for this CBUF - bits [19:4] | RW | 0x0 |
3:0 | RESERVED | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0300 + (k*8); k = 0 to 11 | ||
Physical Address | 0x4880 4300 + (k*8) | Instance | OCMC_RAM1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ADDR | Last virtual write address accessing CBUF | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0304 + (k*8); k = 0 to 11 | ||
Physical Address | 0x4880 4304 + (k*8) | Instance | OCMC_RAM1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ADDR | Last virtual read address accessing CBUF | R | 0x0 |
On-Chip Memory (OCM) Subsystem |
Address Offset | 0x0000 0360 | ||
Physical Address | 0x4880 4360 | Instance | OCMC_RAM1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ADDR | Last Illegal OCMC Address. This register returns the OCMC L3_MAIN address of the last access that was invalidated due to an OUT_OF_RANGE_ERR_FOUND (non-VBUF address) error or any one of the CBUF related access errors (including any write access disabled during overflow error handling). | R | 0x0 |
On-Chip Memory (OCM) Subsystem |