SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4B22 0000 0x4B2A 0000 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | Revision ID Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | IP Revision | R | 0x-(1) |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4B22 0004 0x4B2A 0004 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Control Register holds global control parameters and can forces a soft reset on the module. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRIORITY_HOLD_MODE | NEST_MODE | WAKEUP_MODE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:5 | RESERVED | R | 0x00000 | |
4 | PRIORITY_HOLD_MODE | Reserved | RW | 0x0 |
3:2 | NEST_MODE | The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting | RW | 0x0 |
1 | WAKEUP_MODE | Reserved | RW | 0x0 |
0 | RESERVED | R | 0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4B22 0010 0x4B2A 0010 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_HINT_ANY |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0000 000 | |
0 | ENABLE_HINT_ANY | The current global enable value when read. Writes set the global enable. | RW | 0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4B22 001C 0x4B2A 001C | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTO_OVERRIDE | RESERVED | GLB_NEST_LEVEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | AUTO_OVERRIDE | Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data. | W | 0x0 |
30:9 | RESERVED | R | 0x00000 | |
8:0 | GLB_NEST_LEVEL | The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set. | RW | 0x100 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4B22 0020 0x4B2A 0020 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATUS_SET_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | STATUS_SET_INDEX | Writes set the status of the interrupt given in the index value. Reads return 0. | W | 0x00 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4B22 0024 0x4B2A 0024 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATUS_CLR_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | STATUS_CLR_INDEX | Writes clear the status of the interrupt given in the index value. Reads return 0. | W | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4B22 0028 0x4B2A 0028 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_SET_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | ENABLE_SET_INDEX | Writes set the enable of the interrupt given in the index value. Reads return 0. | W | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4B22 002C 0x4B2A 002C | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_CLR_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | ENABLE_CLR_INDEX | Writes clear the enable of the interrupt given in the index value. Reads return 0. | W | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4B22 0034 0x4B2A 0034 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HINT_ENABLE_SET_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | HINT_ENABLE_SET_INDEX | Writes set the enable of the host interrupt given in the index value. Reads return 0. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4B22 0038 0x4B2A 0038 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HINT_ENABLE_CLR_INDEX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | HINT_ENABLE_CLR_INDEX | Writes clear the enable of the host interrupt given in the index value. Reads return 0. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4B22 0080 0x4B2A 0080 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GLB_NONE | RESERVED | GLB_PRI_INTR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | GLB_NONE | No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending. | R | 0x1 |
30:10 | RESERVED | R | 0x0000 00 | |
9:0 | GLB_PRI_INTR | The currently highest priority interrupt index pending across all the host interrupts. | R | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4B22 0200 0x4B2A 0200 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_STATUS_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RAW_STATUS_31_0 | System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4B22 0204 0x4B2A 0204 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_STATUS_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RAW_STATUS_63_32 | System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0280 | ||
Physical Address | 0x4B22 0280 0x4B2A 0280 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA_STATUS_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENA_STATUS_31_0 | System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0284 | ||
Physical Address | 0x4B22 0284 0x4B2A 0284 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENA_STATUS_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENA_STATUS_63_32 | System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0300 | ||
Physical Address | 0x4B22 0300 0x4B2A 0300 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SET_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENABLE_SET_31_0 | System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0304 | ||
Physical Address | 0x4B22 0304 0x4B2A 0304 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SET_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENABLE_SET_63_32 | System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect. | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0380 | ||
Physical Address | 0x4B22 0380 0x4B2A 0380 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_CLR_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENABLE_CLR_31_0 | System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect. | W | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0384 | ||
Physical Address | 0x4B22 0384 0x4B2A 0384 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_CLR_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ENABLE_CLR_63_32 | System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect. | W | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0400 + (0x4*i) | Index | i = 0 to 15 |
Physical Address | 0x4B22 0400 + (0x4*i) 0x4B2A 0400 + (0x4*i) | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH_MAP_3 | RESERVED | CH_MAP_2 | RESERVED | CH_MAP_1 | RESERVED | CH_MAP_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:24 | CH_MAP_3 | Sets the channel for the system interrupt (k+3). Where k=i*4 | RW | 0x0 |
23:20 | RESERVED | R | 0x0 | |
19:16 | CH_MAP_2 | Sets the channel for the system interrupt (k+2). Where k=i*4 | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:8 | CH_MAP_1 | Sets the channel for the system interrupt (k+1). Where k=i*4 | RW | 0x0 |
7:4 | RESERVED | R | 0x0 | |
3:0 | CH_MAP_0 | Sets the channel for the system interrupt k. Where k=i*4 | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0800 | ||
Physical Address | 0x4B22 0800 0x4B2A 0800 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HINT_MAP_3 | RESERVED | HINT_MAP_2 | RESERVED | HINT_MAP_1 | RESERVED | HINT_MAP_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:24 | HINT_MAP_3 | HOST INTERRUPT MAP FOR CHANNEL 3 | RW | 0x0 |
23:20 | RESERVED | R | 0x0 | |
19:16 | HINT_MAP_2 | HOST INTERRUPT MAP FOR CHANNEL 2 | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:8 | HINT_MAP_1 | HOST INTERRUPT MAP FOR CHANNEL 1 | RW | 0x0 |
7:4 | RESERVED | R | 0x0 | |
3:0 | HINT_MAP_0 | HOST INTERRUPT MAP FOR CHANNEL 0 | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0804 | ||
Physical Address | 0x4B22 0804 0x4B2A 0804 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HINT_MAP_7 | RESERVED | HINT_MAP_6 | RESERVED | HINT_MAP_5 | RESERVED | HINT_MAP_4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:24 | HINT_MAP_7 | HOST INTERRUPT MAP FOR CHANNEL 7 | RW | 0x0 |
23:20 | RESERVED | R | 0x0 | |
19:16 | HINT_MAP_6 | HOST INTERRUPT MAP FOR CHANNEL 6 | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:8 | HINT_MAP_5 | HOST INTERRUPT MAP FOR CHANNEL 5 | RW | 0x0 |
7:4 | RESERVED | R | 0x0 | |
3:0 | HINT_MAP_4 | HOST INTERRUPT MAP FOR CHANNEL 4 | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0808 | ||
Physical Address | 0x4B22 0808 0x4B2A 0808 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HINT_MAP_9 | RESERVED | HINT_MAP_8 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x00000 | |
11:8 | HINT_MAP_9 | HOST INTERRUPT MAP FOR CHANNEL 9 | RW | 0x0 |
7:4 | RESERVED | R | 0x0 | |
3:0 | HINT_MAP_8 | HOST INTERRUPT MAP FOR CHANNEL 8 | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0900 + (0x4*j) | Index | j = 0 to 9 |
Physical Address | 0x4B22 0900 + (0x4*j) 0x4B2A 0900 + (0x4*j) | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NONE_HINT_j | RESERVED | PRI_HINT_j |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | NONE_HINT | No pending interrupt. | R | 0x1 |
30:10 | RESERVED | R | 0x0000 00 | |
9:0 | PRI_HINT | HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt. | R | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0D00 | ||
Physical Address | 0x4B22 0D00 0x4B2A 0D00 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POLARITY_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | POLARITY_31_0 | Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high. | RW | 0x1 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0D04 | ||
Physical Address | 0x4B22 0D04 0x4B2A 0D04 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POLARITY_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | POLARITY_63_32 | Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high. | RW | 0x1 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0D80 | ||
Physical Address | 0x4B22 0D80 0x4B2A 0D80 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE_31_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TYPE_31_0 | Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect). | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 0D84 | ||
Physical Address | 0x4B22 0D84 0x4B2A 0D84 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE_63_32 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TYPE_63_32 | Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect). | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 1100 + 0x4 * j | Index | j=0 to 9 |
Physical Address | 0x4B22 1100 + (0x4*j) 0x4B2A 1100 + (0x4*j) | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTO_OVERRIDE | RESERVED | NEST_HINT_j |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | AUTO_OVERRIDE | Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data. | W | 0x0 |
30:9 | RESERVED | R | 0x00000 | |
8:0 | NEST_HINT | Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used. | RW | 0x100 |
PRU-ICSS Local Interrupt Controller |
Address Offset | 0x0000 1500 | ||
Physical Address | 0x4B22 1500 0x4B2A 1500 | Instance | PRUSS1_INTC PRUSS2_INTC |
Description | The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_HINT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0000 00 | |
9:0 | ENABLE_HINT | The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled | RW | 0x0 |
PRU-ICSS Local Interrupt Controller |