SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
MPU_C0 changes power states only when the StandbyWFI signal is asserted. There is no signal coming from the MPU core, or the MPU_CLUSTER to define in which power state MPU_C0 can go. Software must program such information by writing to the PM_CPU0_PWRSTCTRL[1:0] POWERSTATE bit field before executing the WFI instruction. Table 4-5 provides the software requirements before executing the WFI instruction, and the condition to return to RUN mode.
Low-Power State | Software Sequence Before Executing WFI | Wakeup (Transition Back to Run Mode) |
---|---|---|
WFI/ON Logic ON L1$ ON | Execute a Data Synchronization Barrier (DSB) instruction. | Managed locally to MPU_C0 upon one of the following sources:
|
WFI/INACT Logic ON L1$ ON | Execute a DSB instruction. | Managed locally by MPU_PRCM upon following source:
|
WFI/RETENTION Logic RET L1$ ON L1$ peripheral OFF |
| Managed locally by MPU_PRCM upon following source:
MPU_PRCM does not need to reset MPU_C0. |
For the description of the Cortex-A15 CPU registers and the DSB/ISB instructions, see the Arm Cortex-A15 Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).
The RETENTION low-power state is not natively supported by the MPU_CLUSTER. This mode is implemented with SR3-APG power-management technology. In this mode, the MPU_C0 logic is in full retention with all memory content preserved by keeping the array of memories fully powered and the logic of the memory peripheries shut down. In slow wake-up mode, memories are put into retention to prevent more leakage.
In RETENTION low-power state, the standby controller gates the clock to the MPU_CLUSTER by deasserting the CLKEN signal before signaling the MPU_PRCM to perform a power transition. In this low-power state, the MPU core can be wakened only by the MPU_PRCM. A number of important actions must be performed by software before entering such a state.
A wakeup from RETENTION low-power state does not need to happen through a MPU core reset because MPU core logics are fully retained.
Table 4-6 gives details of the power state of the supported MPU_C0 and the corresponding values of the MPU_PRCM register.
Hardware Conditions | MPU_C0 Programming Model | Resulting MPU_C0 State | |||||
---|---|---|---|---|---|---|---|
StandbyWFI StandbyWFE | State of L2 | MPU_PRCM Power State PM_CPU0_PWRSTCTRL[1:0] POWERSTATE | MPU_PRCM Clock Transition Control CM_CPU0_CLKSTCTRL[1:0] CLKTRCTRL | Logic | L1 Cache | Arm Cortex-A15 Internal Clock | Power State at MPU_PRCM |
MPU_C0 running | Any | Any | Any | ON | ON | ON | ON |
MPU_C0 in WFE | Any | Any | Any | ON | ON | OFF | ON |
MPU_C0 in WFI | Any | Any | NO_SLEEP/SW_WKUP | ON | ON | OFF | ON |
MPU_C0 in WFI | Any | ON | HW_AUTO | ON | ON | OFF | ON |
MPU_C0 in WFI | != (IDLE/WFI/WFI) | Any | HW_AUTO | ON | ON | OFF | ON |
MPU_C0 in WFI | IDLE/WFI/WFI | INACT | HW_AUTO | ON | ON | OFF | INACT |
MPU_C0 in WFI | IDLE/WFI/WFI | RETENTION | HW_AUTO | SR3-APG/ ON(1) | ON/RETENTION(2) | OFF | CSWRET |
The PM_CPU0_PWRSTCTRL register is static over any power transition. That is, software programs it before executing the WFI instruction and does not change it until MPU_C0 is again in running mode. In other words, when MPU_C0 reaches a low-power state, it cannot move to another low-power state. It must be woken up to reach another low-power state. To wake up MPU_C0, the user must: