SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4A00 5300 | Instance | CM_CORE_AON__MPU |
Description | This register enables the MPU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKACTIVITY_MPU_GCLK | RESERVED | CLKTRCTRL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:9 | RESERVED | R | 0x0 | |
8 | CLKACTIVITY_MPU_GCLK | This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive] | R | 0x0 |
0x0: Corresponding clock is definitely gated | ||||
0x1: Corresponding clock is running or gating/ungating transition is on-going | ||||
7:2 | RESERVED | R | 0x0 | |
1:0 | CLKTRCTRL | Controls the clock state transition of the MPU clock domain. | RW | 0x0 |
0x0: NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur. | ||||
0x1: Reserved | ||||
0x2: SW_WKUP: Start a software forced wake-up transition on the domain. | ||||
0x3: HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions. |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4A00 5304 | Instance | CM_CORE_AON__MPU |
Description | This register controls the static domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having system initiator(s). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PCIE_STATDEP | VPE_STATDEP | L4PER3_STATDEP | L4PER2_STATDEP | GMAC_STATDEP | IPU_STATDEP | IPU1_STATDEP | EVE4_STATDEP | EVE3_STATDEP | EVE2_STATDEP | EVE1_STATDEP | DSP2_STATDEP | CUSTEFUSE_STATDEP | COREAON_STATDEP | WKUPAON_STATDEP | L4SEC_STATDEP | L4PER_STATDEP | L4CFG_STATDEP | SDMA_STATDEP | GPU_STATDEP | CAM_STATDEP | DSS_STATDEP | L3INIT_STATDEP | RESERVED | L3MAIN1_STATDEP | EMIF_STATDEP | RESERVED | IVA_STATDEP | DSP1_STATDEP | IPU2_STATDEP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | PCIE_STATDEP | Static dependency towards PCIE clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
28 | VPE_STATDEP | Static dependency towards VPE clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
27 | L4PER3_STATDEP | Static dependency towards L4PER3 clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
26 | L4PER2_STATDEP | Static dependency towards L4PER2 clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
25 | GMAC_STATDEP | Static dependency towards GMAC clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
24 | IPU_STATDEP | Static dependency towards IPU clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
23 | IPU1_STATDEP | Static dependency towards IPU1 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
22 | EVE4_STATDEP | Static dependency towards EVE4 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
21 | EVE3_STATDEP | Static dependency towards EVE3 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
20 | EVE2_STATDEP | Static dependency towards EVE2 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
19 | EVE1_STATDEP | Static dependency towards EVE1 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
18 | DSP2_STATDEP | Static dependency towards DSP2 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
17 | CUSTEFUSE_STATDEP | Static dependency towards CUSTEFUSE clock domain | R | 0x0 |
0x0: Dependency is disabled | ||||
16 | COREAON_STATDEP | Static dependency towards COREAON clock domain | R | 0x0 |
0x0: Dependency is disabled | ||||
15 | WKUPAON_STATDEP | Static dependency towards WKUPAON clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
14 | L4SEC_STATDEP | Static dependency towards L4SEC clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
13 | L4PER_STATDEP | Static dependency towards L4PER clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
12 | L4CFG_STATDEP | Static dependency towards L4CFG clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
11 | SDMA_STATDEP | Static dependency towards SDMA clock domain | R | 0x0 |
0x0: Dependency is disabled | ||||
10 | GPU_STATDEP | Static dependency towards GPU clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
9 | CAM_STATDEP | Static dependency towards CAM clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
8 | DSS_STATDEP | Static dependency towards DSS clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
7 | L3INIT_STATDEP | Static dependency towards L3INIT clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
6 | RESERVED | R | 0x0 | |
5 | L3MAIN1_STATDEP | Static dependency towards L3MAIN clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
4 | EMIF_STATDEP | Static dependency towards EMIF clock domain | RW | 0x1 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
3 | RESERVED | R | 0x0 | |
2 | IVA_STATDEP | Static dependency towards IVA clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
1 | DSP1_STATDEP | Static dependency towards DSP1 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled | ||||
0 | IPU2_STATDEP | Static dependency towards IPU2 clock domain | RW | 0x0 |
0x0: Dependency is disabled | ||||
0x1: Dependency is enabled |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4A00 5308 | Instance | CM_CORE_AON__MPU |
Description | This register controls the dynamic domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having OCP master port(s). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WINDOWSIZE | RESERVED | L3MAIN1_DYNDEP | EMIF_DYNDEP | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:24 | WINDOWSIZE | Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined by CM_DYN_DEP_PRESCAL register. | RW | 0x4 |
23:6 | RESERVED | R | 0x0 | |
5 | L3MAIN1_DYNDEP | Dynamic dependency towards L3MAIN1 clock domain | R | 0x1 |
0x1: Dependency is enabled | ||||
4 | EMIF_DYNDEP | Dynamic dependency towards EMIF clock domain | R | 0x1 |
0x1: Dependency is enabled | ||||
3:0 | RESERVED | R | 0x0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4A00 5320 | Instance | CM_CORE_AON__MPU |
Description | This register manages the MPU clocks. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKSEL_ABE_DIV_MODE | CLKSEL_EMIF_DIV_MODE | RESERVED | STBYST | IDLEST | RESERVED | MODULEMODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:27 | RESERVED | R | 0x0 | |
26 | CLKSEL_ABE_DIV_MODE | Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock | RW | 0x0 |
0x0: MPU DPLL clock divided by 8 | ||||
0x1: MPU DPLL clock divided by 16 | ||||
25:24 | CLKSEL_EMIF_DIV_MODE | Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock | RW | 0x0 |
0x0: MPU DPLL clock divided by 4 | ||||
0x1: MPU DPLL clock divided by 4 | ||||
0x2: MPU DPLL clock divided by 8 | ||||
0x3: MPU DPLL clock divided by 8 | ||||
23:19 | RESERVED | R | 0x0 | |
18 | STBYST | Module standby status. [warm reset insensitive] | R | 0x1 |
0x0: Module is functional (not in standby) | ||||
0x1: Module is in standby | ||||
17:16 | IDLEST | Module idle status. [warm reset insensitive] | R | 0x3 |
0x0: Module is fully functional, including OCP | ||||
0x1: Module is performing transition: wakeup, or sleep, or sleep abortion | ||||
0x2: Module is in Idle mode (only OCP part). It is functional if using separate functional clock | ||||
0x3: Module is disabled and cannot be accessed | ||||
15:2 | RESERVED | R | 0x0 | |
1:0 | MODULEMODE | Control the way mandatory clocks are managed. | R | 0x1 |
0x1: Module is managed automatically by HW according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. Module clocks may be gated according to the clock domain state. |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4A00 5328 | Instance | CM_CORE_AON__MPU |
Description | This register manages the MPU_MPU_DBG clocks. [warm reset insensitive] | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEST | RESERVED | MODULEMODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:18 | RESERVED | R | 0x0 | |
17:16 | IDLEST | Module idle status | R | 0x3 |
0x0: Module is fully functional, including OCP | ||||
0x1: Module is performing transition: wakeup, or sleep, or sleep abortion | ||||
0x2: Module is in Idle mode (only OCP part). It is functional if using separate functional clock | ||||
0x3: Module is disabled and cannot be accessed | ||||
15:2 | RESERVED | R | 0x0 | |
1:0 | MODULEMODE | Control the way mandatory clocks are managed. | R | 0x1 |
0x1: Module is managed automatically by HW according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any OCP access to module is always granted. Module clocks may be gated according to the clock domain state. |